87 lines
2.1 KiB
YAML
87 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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description: |
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The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
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disabled by using the port output enabling function for the GPT (POEG).
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Specifically, either of the following ways can be used.
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* Input level detection of the GTETRGA to GTETRGD pins.
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* Output-disable request from the GPT.
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* SSF bit setting(ie, by setting POEGGn.SSF to 1)
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The state of the GTIOCxA and the GTIOCxB pins when the output is disabled,
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are controlled by the GPT module.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-poeg # RZ/G2{L,LC}
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- renesas,r9a07g054-poeg # RZ/V2L
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- const: renesas,rzg2l-poeg
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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renesas,gpt:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to gpt instance that serves the pwm operation.
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renesas,poeg-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1, 2, 3 ]
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description: |
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POEG group index. Valid values are:
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<0> : POEG group A
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<1> : POEG group B
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<2> : POEG group C
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<3> : POEG group D
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- power-domains
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- resets
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- renesas,poeg-id
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- renesas,gpt
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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poeggd: poeg@10049400 {
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compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
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reg = <0x10049400 0x400>;
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interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_POEG_D_RST>;
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renesas,poeg-id = <3>;
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renesas,gpt = <&gpt>;
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};
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