679 lines
22 KiB
C
679 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP3xxx CM module functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "prm2xxx_3xxx.h"
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#include "cm.h"
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#include "cm3xxx.h"
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#include "cm-regbits-34xx.h"
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#include "clockdomain.h"
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static const u8 omap3xxx_cm_idlest_offs[] = {
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CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
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};
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/*
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*
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*/
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static void _write_clktrctrl(u8 c, s16 module, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= ~mask;
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v |= c << __ffs(mask);
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omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
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}
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static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= mask;
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v >>= __ffs(mask);
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return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
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}
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static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
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}
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static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
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}
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static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
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}
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static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
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}
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/*
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*
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*/
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/**
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* omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
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* @part: PRCM partition, ignored for OMAP3
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* @prcm_mod: PRCM module offset
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* @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
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* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
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*
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* Wait for the PRCM to indicate that the module identified by
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* (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
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* success or -EBUSY if the module doesn't enable in time.
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*/
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static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
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u8 idlest_shift)
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{
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int ena = 0, i = 0;
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u8 cm_idlest_reg;
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u32 mask;
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if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
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return -EINVAL;
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cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
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mask = 1 << idlest_shift;
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ena = 0;
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omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
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mask) == ena), MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/**
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* omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
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* @idlest_reg: CM_IDLEST* virtual address
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* @prcm_inst: pointer to an s16 to return the PRCM instance offset
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* @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
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*
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* XXX This function is only needed until absolute register addresses are
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* removed from the OMAP struct clk records.
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*/
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static int omap3xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
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s16 *prcm_inst,
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u8 *idlest_reg_id)
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{
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unsigned long offs;
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u8 idlest_offs;
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int i;
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idlest_offs = idlest_reg->offset & 0xff;
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for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
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if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
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*idlest_reg_id = i + 1;
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break;
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}
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}
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if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
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return -EINVAL;
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offs = idlest_reg->offset;
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offs &= 0xff00;
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*prcm_inst = offs;
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return 0;
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}
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/* Clockdomain low-level operations */
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static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP,
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(1 << clkdm2->dep_bit));
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}
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static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
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{
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struct clkdm_dep *cd;
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u32 mask = 0;
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for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
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if (!cd->clkdm)
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continue; /* only happens if data is erroneous */
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mask |= 1 << cd->clkdm->dep_bit;
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cd->sleepdep_usecount = 0;
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}
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omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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return 0;
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}
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static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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return 0;
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}
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static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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if (clkdm->usecount > 0)
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clkdm_add_autodeps(clkdm);
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (clkdm->usecount > 0)
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clkdm_del_autodeps(clkdm);
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}
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static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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/*
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* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
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* more details on the unpleasant problem this is working
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* around
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*/
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if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
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(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
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omap3xxx_clkdm_wakeup(clkdm);
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return 0;
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}
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hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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clkdm_add_autodeps(clkdm);
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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omap3xxx_clkdm_wakeup(clkdm);
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}
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return 0;
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}
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static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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/*
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* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
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* more details on the unpleasant problem this is working
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* around
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*/
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if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
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!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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return 0;
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}
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hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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clkdm_del_autodeps(clkdm);
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
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omap3xxx_clkdm_sleep(clkdm);
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}
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return 0;
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}
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struct clkdm_ops omap3_clkdm_operations = {
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.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
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.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
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.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
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.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
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.clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep,
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.clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep,
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.clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep,
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.clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps,
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.clkdm_sleep = omap3xxx_clkdm_sleep,
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.clkdm_wakeup = omap3xxx_clkdm_wakeup,
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.clkdm_allow_idle = omap3xxx_clkdm_allow_idle,
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.clkdm_deny_idle = omap3xxx_clkdm_deny_idle,
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.clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
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.clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
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};
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/*
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* Context save/restore code - OMAP3 only
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*/
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struct omap3_cm_regs {
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u32 iva2_cm_clksel1;
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u32 iva2_cm_clksel2;
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u32 cm_sysconfig;
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u32 sgx_cm_clksel;
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u32 dss_cm_clksel;
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u32 cam_cm_clksel;
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u32 per_cm_clksel;
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u32 emu_cm_clksel;
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u32 emu_cm_clkstctrl;
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u32 pll_cm_autoidle;
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u32 pll_cm_autoidle2;
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u32 pll_cm_clksel4;
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u32 pll_cm_clksel5;
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u32 pll_cm_clken2;
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u32 cm_polctrl;
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u32 iva2_cm_fclken;
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u32 iva2_cm_clken_pll;
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u32 core_cm_fclken1;
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u32 core_cm_fclken3;
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u32 sgx_cm_fclken;
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u32 wkup_cm_fclken;
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u32 dss_cm_fclken;
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u32 cam_cm_fclken;
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u32 per_cm_fclken;
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u32 usbhost_cm_fclken;
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u32 core_cm_iclken1;
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u32 core_cm_iclken2;
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u32 core_cm_iclken3;
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u32 sgx_cm_iclken;
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u32 wkup_cm_iclken;
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u32 dss_cm_iclken;
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u32 cam_cm_iclken;
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u32 per_cm_iclken;
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u32 usbhost_cm_iclken;
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u32 iva2_cm_autoidle2;
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u32 mpu_cm_autoidle2;
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u32 iva2_cm_clkstctrl;
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u32 mpu_cm_clkstctrl;
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u32 core_cm_clkstctrl;
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u32 sgx_cm_clkstctrl;
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u32 dss_cm_clkstctrl;
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u32 cam_cm_clkstctrl;
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u32 per_cm_clkstctrl;
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u32 neon_cm_clkstctrl;
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u32 usbhost_cm_clkstctrl;
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u32 core_cm_autoidle1;
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u32 core_cm_autoidle2;
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u32 core_cm_autoidle3;
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u32 wkup_cm_autoidle;
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u32 dss_cm_autoidle;
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u32 cam_cm_autoidle;
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u32 per_cm_autoidle;
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u32 usbhost_cm_autoidle;
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u32 sgx_cm_sleepdep;
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u32 dss_cm_sleepdep;
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u32 cam_cm_sleepdep;
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u32 per_cm_sleepdep;
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u32 usbhost_cm_sleepdep;
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u32 cm_clkout_ctrl;
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};
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static struct omap3_cm_regs cm_context;
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void omap3_cm_save_context(void)
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{
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cm_context.iva2_cm_clksel1 =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
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cm_context.iva2_cm_clksel2 =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
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cm_context.cm_sysconfig =
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omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
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cm_context.sgx_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
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cm_context.dss_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
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cm_context.cam_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
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cm_context.per_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
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cm_context.emu_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
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cm_context.emu_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
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* In this case, even though this register has been saved in
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* scratchpad contents, we need to restore AUTO_PERIPH_DPLL
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* by ourselves. So, we need to save it anyway.
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*/
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cm_context.pll_cm_autoidle =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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cm_context.pll_cm_autoidle2 =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
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cm_context.pll_cm_clksel4 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
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cm_context.pll_cm_clksel5 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
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cm_context.pll_cm_clken2 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
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cm_context.cm_polctrl =
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omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
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cm_context.iva2_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
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cm_context.iva2_cm_clken_pll =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
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cm_context.core_cm_fclken1 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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cm_context.core_cm_fclken3 =
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omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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cm_context.sgx_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
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cm_context.wkup_cm_fclken =
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omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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cm_context.dss_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
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cm_context.cam_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
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cm_context.per_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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cm_context.usbhost_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
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|
cm_context.core_cm_iclken1 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
|
|
cm_context.core_cm_iclken2 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
|
|
cm_context.core_cm_iclken3 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
|
|
cm_context.sgx_cm_iclken =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
|
|
cm_context.wkup_cm_iclken =
|
|
omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
|
|
cm_context.dss_cm_iclken =
|
|
omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
|
|
cm_context.cam_cm_iclken =
|
|
omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
|
|
cm_context.per_cm_iclken =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
|
|
cm_context.usbhost_cm_iclken =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
|
|
cm_context.iva2_cm_autoidle2 =
|
|
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
|
|
cm_context.mpu_cm_autoidle2 =
|
|
omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
|
|
cm_context.iva2_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.mpu_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.core_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.sgx_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.dss_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.cam_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.per_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.neon_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_context.usbhost_cm_clkstctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_context.core_cm_autoidle1 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
|
|
cm_context.core_cm_autoidle2 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
|
|
cm_context.core_cm_autoidle3 =
|
|
omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
|
|
cm_context.wkup_cm_autoidle =
|
|
omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
|
|
cm_context.dss_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
|
|
cm_context.cam_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
|
|
cm_context.per_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
|
|
cm_context.usbhost_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
cm_context.sgx_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_context.dss_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.cam_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.per_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.usbhost_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_context.cm_clkout_ctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
}
|
|
|
|
void omap3_cm_restore_context(void)
|
|
{
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL1);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL2);
|
|
omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
|
|
OMAP3430_CM_SYSCONFIG);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
|
|
CM_CLKSEL1);
|
|
omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
/*
|
|
* As per erratum i671, ROM code does not respect the PER DPLL
|
|
* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
|
|
* In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
|
|
*/
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL4);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL5);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKEN2);
|
|
omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
|
|
OMAP3430_CM_POLCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
|
|
OMAP3430_CM_CLKEN_PLL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
|
|
CM_FCLKEN1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
|
|
OMAP3430ES2_CM_FCLKEN3);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
|
|
CM_ICLKEN1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
|
|
CM_ICLKEN2);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
|
|
CM_ICLKEN3);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
|
|
CM_AUTOIDLE1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
|
|
CM_AUTOIDLE3);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
|
|
OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
}
|
|
|
|
void omap3_cm_save_scratchpad_contents(u32 *ptr)
|
|
{
|
|
*ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
|
|
*ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
|
|
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
|
|
|
/*
|
|
* As per erratum i671, ROM code does not respect the PER DPLL
|
|
* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
|
|
* Then, in any case, clear these bits to avoid extra latencies.
|
|
*/
|
|
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
|
|
~OMAP3430_AUTO_PERIPH_DPLL_MASK;
|
|
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
|
|
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
|
|
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
|
|
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
|
|
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
|
|
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
|
|
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
|
|
static const struct cm_ll_data omap3xxx_cm_ll_data = {
|
|
.split_idlest_reg = &omap3xxx_cm_split_idlest_reg,
|
|
.wait_module_ready = &omap3xxx_cm_wait_module_ready,
|
|
};
|
|
|
|
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
|
|
{
|
|
omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
|
|
OMAP3430_IVA2_MOD);
|
|
return cm_register(&omap3xxx_cm_ll_data);
|
|
}
|
|
|
|
static void __exit omap3xxx_cm_exit(void)
|
|
{
|
|
cm_unregister(&omap3xxx_cm_ll_data);
|
|
}
|
|
__exitcall(omap3xxx_cm_exit);
|