179 lines
5.4 KiB
C
179 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
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*
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* Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Paul Walmsley
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
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#define __ARCH_ARM_MACH_OMAP2_PRM_H
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#include "prcm-common.h"
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# ifndef __ASSEMBLER__
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extern struct omap_domain_base prm_base;
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extern u16 prm_features;
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int omap_prcm_init(void);
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int omap2_prcm_base_init(void);
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# endif
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/*
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* prm_features flag values
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*
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* PRM_HAS_IO_WAKEUP: has IO wakeup capability
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* PRM_HAS_VOLTAGE: has voltage domains
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*/
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#define PRM_HAS_IO_WAKEUP BIT(0)
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#define PRM_HAS_VOLTAGE BIT(1)
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/*
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* MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
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* module to softreset
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*/
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#define MAX_MODULE_SOFTRESET_WAIT 10000
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/*
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* MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
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* submodule to exit hardreset
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*/
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#define MAX_MODULE_HARDRESET_WAIT 10000
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/*
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* Register bitfields
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*/
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/*
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* 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_INTRANSITION_MASK (1 << 20)
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/*
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* 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_POWERSTATEST_SHIFT 0
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#define OMAP_POWERSTATEST_MASK (0x3 << 0)
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/*
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* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSP, PM_PWSTST_MPU
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*
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* 2430: PM_PWSTCTRL_MDM shared bits
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*
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* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
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* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
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* PM_PWSTCTRL_NEON shared bits
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*/
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#define OMAP_POWERSTATE_SHIFT 0
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#define OMAP_POWERSTATE_MASK (0x3 << 0)
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/*
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* Standardized OMAP reset source bits
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*
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* To the extent these happen to match the hardware register bit
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* shifts, it's purely coincidental. Used by omap-wdt.c.
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* OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
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* there are any bits remaining in the global PRM_RSTST register that
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* haven't been identified, or when the PRM code for the current SoC
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* doesn't know how to interpret the register.
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*/
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#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
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#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
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#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
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#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
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#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
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#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
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#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
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#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
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#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
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#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
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#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
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#define OMAP_C2C_RST_SRC_ID_SHIFT 11
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#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
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#ifndef __ASSEMBLER__
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/**
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* struct prm_reset_src_map - map register bitshifts to standard bitshifts
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* @reg_shift: bitshift in the PRM reset source register
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* @std_shift: bitshift equivalent in the standard reset source list
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*
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* The fields are signed because -1 is used as a terminator.
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*/
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struct prm_reset_src_map {
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s8 reg_shift;
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s8 std_shift;
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};
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/**
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* struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
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* @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
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* @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
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* @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
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* @late_init: ptr to the late init function
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* @assert_hardreset: ptr to the SoC PRM hardreset assert impl
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* @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
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*
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* XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
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* deprecated.
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*/
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struct prm_ll_data {
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u32 (*read_reset_sources)(void);
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bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
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void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
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int (*late_init)(void);
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int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
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int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
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u16 offset, u16 st_offset);
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int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
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u16 offset);
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void (*reset_system)(void);
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int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
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u32 (*vp_check_txdone)(u8 vp_id);
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void (*vp_clear_txdone)(u8 vp_id);
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};
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extern int prm_register(struct prm_ll_data *pld);
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extern int prm_unregister(struct prm_ll_data *pld);
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int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
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int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
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u16 offset, u16 st_offset);
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int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
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extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
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extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
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void omap_prm_reset_system(void);
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int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
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/*
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* Voltage Processor (VP) identifiers
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*/
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#define OMAP3_VP_VDD_MPU_ID 0
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#define OMAP3_VP_VDD_CORE_ID 1
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#define OMAP4_VP_VDD_CORE_ID 0
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#define OMAP4_VP_VDD_IVA_ID 1
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#define OMAP4_VP_VDD_MPU_ID 2
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u32 omap_prm_vp_check_txdone(u8 vp_id);
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void omap_prm_vp_clear_txdone(u8 vp_id);
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#endif
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#endif
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