413 lines
9.3 KiB
Plaintext
413 lines
9.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Amazon's Annapurna Labs Alpine v3";
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compatible = "amazon,al-alpine-v3";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x1>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x2>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x3>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x100>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x101>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x102>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x103>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x200>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x201>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x202>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x203>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x300>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster3_l2>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x301>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster3_l2>;
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};
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cpu@302 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x302>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster3_l2>;
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};
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cpu@303 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x303>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: cache@0 {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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cache-unified;
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};
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cluster1_l2: cache@100 {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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cache-unified;
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};
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cluster2_l2: cache@200 {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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cache-unified;
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};
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cluster3_l2: cache@300 {
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compatible = "cache";
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-level = <2>;
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cache-unified;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@0 {
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reg = <0x0 0x0 0x0 0x100000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f0000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0xf0800000 0 0x10000>, /* GICD */
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<0x0 0xf0a00000 0 0x200000>, /* GICR */
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<0x0 0xf0000000 0 0x2000>, /* GICC */
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<0x0 0xf0010000 0 0x1000>, /* GICH */
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<0x0 0xf0020000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie@fbd00000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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reg = <0x0 0xfbd00000 0x0 0x100000>;
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interrupt-map-mask = <0xf800 0 0 7>;
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/* 8 x legacy interrupts for SATA only */
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interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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<0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
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<0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
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<0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
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<0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
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<0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
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<0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
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<0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
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ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
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bus-range = <0x00 0x00>;
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msi-parent = <&msix>;
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};
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msix: msix@fbe00000 {
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compatible = "al,alpine-msix";
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reg = <0x0 0xfbe00000 0x0 0x100000>;
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interrupt-controller;
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msi-controller;
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al,msi-base-spi = <336>;
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al,msi-num-spis = <959>;
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interrupt-parent = <&gic>;
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};
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io-fabric {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xfc000000 0x2000000>;
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uart0: serial@1883000 {
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compatible = "ns16550a";
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reg = <0x1883000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>; /* Filled by firmware */
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@1884000 {
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compatible = "ns16550a";
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reg = <0x1884000 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>; /* Filled by firmware */
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@1885000 {
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compatible = "ns16550a";
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reg = <0x1885000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>; /* Filled by firmware */
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@1886000 {
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compatible = "ns16550a";
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reg = <0x1886000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>; /* Filled by firmware */
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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};
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};
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};
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