linux-zen-desktop/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3566-anbernic-rgxx3.dtsi"
/ {
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc_sys>;
pwms = <&pwm4 0 25000 0>;
};
};
&cru {
assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
<&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
assigned-clock-rates = <32768>, <1200000000>,
<200000000>, <241500000>;
};
&dsi_dphy0 {
status = "okay";
};
&dsi0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
ports {
dsi0_in: port@0 {
reg = <0>;
dsi0_in_vp1: endpoint {
remote-endpoint = <&vp1_out_dsi0>;
};
};
dsi0_out: port@1 {
reg = <1>;
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};
};
panel: panel@0 {
compatible = "anbernic,rg353p-panel", "newvision,nv3051d";
reg = <0>;
backlight = <&backlight>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst>;
reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc3v3_lcd0_n>;
port {
mipi_in_panel: endpoint {
remote-endpoint = <&mipi_out_panel>;
};
};
};
};
&gpio_keys_control {
button-a {
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
label = "EAST";
linux,code = <BTN_EAST>;
};
button-left {
gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
label = "DPAD-LEFT";
linux,code = <BTN_DPAD_LEFT>;
};
button-right {
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
label = "DPAD-RIGHT";
linux,code = <BTN_DPAD_RIGHT>;
};
button-y {
gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
label = "WEST";
linux,code = <BTN_WEST>;
};
};
&i2c0 {
/* This hardware is physically present but unused. */
power-monitor@62 {
compatible = "cellwise,cw2015";
reg = <0x62>;
status = "disabled";
};
};
&pinctrl {
gpio-lcd {
lcd_rst: lcd-rst {
rockchip,pins =
<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm4 {
status = "okay";
};
&vp1 {
vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
reg = <ROCKCHIP_VOP2_EP_MIPI0>;
remote-endpoint = <&dsi0_in_vp1>;
};
};