901 lines
22 KiB
C
901 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Exception handling code
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*
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* Copyright (C) 2019 ARM Ltd.
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*/
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#include <linux/context_tracking.h>
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#include <linux/kasan.h>
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#include <linux/linkage.h>
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#include <linux/lockdep.h>
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#include <linux/ptrace.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/thread_info.h>
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#include <asm/cpufeature.h>
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#include <asm/daifflags.h>
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#include <asm/esr.h>
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#include <asm/exception.h>
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#include <asm/irq_regs.h>
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#include <asm/kprobes.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/sdei.h>
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#include <asm/stacktrace.h>
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#include <asm/sysreg.h>
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#include <asm/system_misc.h>
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/*
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* Handle IRQ/context state management when entering from kernel mode.
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* Before this function is called it is not safe to call regular kernel code,
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* instrumentable code, or any code which may trigger an exception.
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*
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* This is intended to match the logic in irqentry_enter(), handling the kernel
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* mode transitions only.
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*/
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static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs)
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{
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regs->exit_rcu = false;
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if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
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lockdep_hardirqs_off(CALLER_ADDR0);
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ct_irq_enter();
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trace_hardirqs_off_finish();
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regs->exit_rcu = true;
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return;
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}
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lockdep_hardirqs_off(CALLER_ADDR0);
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rcu_irq_enter_check_tick();
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trace_hardirqs_off_finish();
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}
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static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
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{
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__enter_from_kernel_mode(regs);
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mte_check_tfsr_entry();
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mte_disable_tco_entry(current);
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}
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/*
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* Handle IRQ/context state management when exiting to kernel mode.
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* After this function returns it is not safe to call regular kernel code,
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* instrumentable code, or any code which may trigger an exception.
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*
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* This is intended to match the logic in irqentry_exit(), handling the kernel
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* mode transitions only, and with preemption handled elsewhere.
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*/
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static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
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{
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lockdep_assert_irqs_disabled();
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if (interrupts_enabled(regs)) {
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if (regs->exit_rcu) {
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trace_hardirqs_on_prepare();
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lockdep_hardirqs_on_prepare();
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ct_irq_exit();
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lockdep_hardirqs_on(CALLER_ADDR0);
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return;
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}
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trace_hardirqs_on();
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} else {
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if (regs->exit_rcu)
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ct_irq_exit();
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}
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}
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static void noinstr exit_to_kernel_mode(struct pt_regs *regs)
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{
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mte_check_tfsr_exit();
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__exit_to_kernel_mode(regs);
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}
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/*
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* Handle IRQ/context state management when entering from user mode.
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* Before this function is called it is not safe to call regular kernel code,
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* instrumentable code, or any code which may trigger an exception.
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*/
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static __always_inline void __enter_from_user_mode(void)
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{
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lockdep_hardirqs_off(CALLER_ADDR0);
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CT_WARN_ON(ct_state() != CONTEXT_USER);
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user_exit_irqoff();
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trace_hardirqs_off_finish();
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mte_disable_tco_entry(current);
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}
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static __always_inline void enter_from_user_mode(struct pt_regs *regs)
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{
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__enter_from_user_mode();
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}
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/*
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* Handle IRQ/context state management when exiting to user mode.
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* After this function returns it is not safe to call regular kernel code,
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* instrumentable code, or any code which may trigger an exception.
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*/
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static __always_inline void __exit_to_user_mode(void)
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{
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trace_hardirqs_on_prepare();
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lockdep_hardirqs_on_prepare();
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user_enter_irqoff();
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lockdep_hardirqs_on(CALLER_ADDR0);
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}
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static __always_inline void exit_to_user_mode_prepare(struct pt_regs *regs)
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{
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unsigned long flags;
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local_daif_mask();
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flags = read_thread_flags();
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if (unlikely(flags & _TIF_WORK_MASK))
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do_notify_resume(regs, flags);
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lockdep_sys_exit();
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}
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static __always_inline void exit_to_user_mode(struct pt_regs *regs)
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{
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exit_to_user_mode_prepare(regs);
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mte_check_tfsr_exit();
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__exit_to_user_mode();
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}
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asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs)
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{
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exit_to_user_mode(regs);
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}
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/*
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* Handle IRQ/context state management when entering an NMI from user/kernel
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* mode. Before this function is called it is not safe to call regular kernel
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* code, instrumentable code, or any code which may trigger an exception.
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*/
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static void noinstr arm64_enter_nmi(struct pt_regs *regs)
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{
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regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
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__nmi_enter();
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lockdep_hardirqs_off(CALLER_ADDR0);
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lockdep_hardirq_enter();
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ct_nmi_enter();
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trace_hardirqs_off_finish();
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ftrace_nmi_enter();
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}
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/*
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* Handle IRQ/context state management when exiting an NMI from user/kernel
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* mode. After this function returns it is not safe to call regular kernel
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* code, instrumentable code, or any code which may trigger an exception.
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*/
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static void noinstr arm64_exit_nmi(struct pt_regs *regs)
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{
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bool restore = regs->lockdep_hardirqs;
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ftrace_nmi_exit();
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if (restore) {
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trace_hardirqs_on_prepare();
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lockdep_hardirqs_on_prepare();
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}
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ct_nmi_exit();
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lockdep_hardirq_exit();
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if (restore)
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lockdep_hardirqs_on(CALLER_ADDR0);
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__nmi_exit();
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}
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/*
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* Handle IRQ/context state management when entering a debug exception from
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* kernel mode. Before this function is called it is not safe to call regular
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* kernel code, instrumentable code, or any code which may trigger an exception.
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*/
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static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
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{
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regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
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lockdep_hardirqs_off(CALLER_ADDR0);
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ct_nmi_enter();
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trace_hardirqs_off_finish();
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}
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/*
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* Handle IRQ/context state management when exiting a debug exception from
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* kernel mode. After this function returns it is not safe to call regular
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* kernel code, instrumentable code, or any code which may trigger an exception.
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*/
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static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
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{
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bool restore = regs->lockdep_hardirqs;
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if (restore) {
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trace_hardirqs_on_prepare();
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lockdep_hardirqs_on_prepare();
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}
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ct_nmi_exit();
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if (restore)
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lockdep_hardirqs_on(CALLER_ADDR0);
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}
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#ifdef CONFIG_PREEMPT_DYNAMIC
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DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
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#define need_irq_preemption() \
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(static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
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#else
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#define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION))
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#endif
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static void __sched arm64_preempt_schedule_irq(void)
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{
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if (!need_irq_preemption())
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return;
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/*
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* Note: thread_info::preempt_count includes both thread_info::count
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* and thread_info::need_resched, and is not equivalent to
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* preempt_count().
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*/
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if (READ_ONCE(current_thread_info()->preempt_count) != 0)
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return;
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/*
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* DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
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* priority masking is used the GIC irqchip driver will clear DAIF.IF
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* using gic_arch_enable_irqs() for normal IRQs. If anything is set in
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* DAIF we must have handled an NMI, so skip preemption.
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*/
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if (system_uses_irq_prio_masking() && read_sysreg(daif))
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return;
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/*
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* Preempting a task from an IRQ means we leave copies of PSTATE
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* on the stack. cpufeature's enable calls may modify PSTATE, but
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* resuming one of these preempted tasks would undo those changes.
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*
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* Only allow a task to be preempted once cpufeatures have been
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* enabled.
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*/
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if (system_capabilities_finalized())
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preempt_schedule_irq();
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}
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static void do_interrupt_handler(struct pt_regs *regs,
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void (*handler)(struct pt_regs *))
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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if (on_thread_stack())
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call_on_irq_stack(regs, handler);
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else
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handler(regs);
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set_irq_regs(old_regs);
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}
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extern void (*handle_arch_irq)(struct pt_regs *);
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extern void (*handle_arch_fiq)(struct pt_regs *);
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static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector,
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unsigned long esr)
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{
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arm64_enter_nmi(regs);
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console_verbose();
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pr_crit("Unhandled %s exception on CPU%d, ESR 0x%016lx -- %s\n",
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vector, smp_processor_id(), esr,
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esr_get_class_string(esr));
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__show_regs(regs);
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panic("Unhandled exception");
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}
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#define UNHANDLED(el, regsize, vector) \
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asmlinkage void noinstr el##_##regsize##_##vector##_handler(struct pt_regs *regs) \
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{ \
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const char *desc = #regsize "-bit " #el " " #vector; \
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__panic_unhandled(regs, desc, read_sysreg(esr_el1)); \
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}
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
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static void cortex_a76_erratum_1463225_svc_handler(void)
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{
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u32 reg, val;
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if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
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return;
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if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
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return;
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
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reg = read_sysreg(mdscr_el1);
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val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
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write_sysreg(val, mdscr_el1);
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asm volatile("msr daifclr, #8");
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isb();
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/* We will have taken a single-step exception by this point */
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write_sysreg(reg, mdscr_el1);
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__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
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}
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static __always_inline bool
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cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
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return false;
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/*
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* We've taken a dummy step exception from the kernel to ensure
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* that interrupts are re-enabled on the syscall path. Return back
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* to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
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* masked so that we can safely restore the mdscr and get on with
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* handling the syscall.
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*/
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regs->pstate |= PSR_D_BIT;
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return true;
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}
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#else /* CONFIG_ARM64_ERRATUM_1463225 */
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static void cortex_a76_erratum_1463225_svc_handler(void) { }
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static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
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{
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return false;
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}
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#endif /* CONFIG_ARM64_ERRATUM_1463225 */
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UNHANDLED(el1t, 64, sync)
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UNHANDLED(el1t, 64, irq)
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UNHANDLED(el1t, 64, fiq)
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UNHANDLED(el1t, 64, error)
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static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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enter_from_kernel_mode(regs);
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local_daif_inherit(regs);
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do_mem_abort(far, esr, regs);
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local_daif_mask();
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exit_to_kernel_mode(regs);
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}
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static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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enter_from_kernel_mode(regs);
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local_daif_inherit(regs);
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do_sp_pc_abort(far, esr, regs);
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local_daif_mask();
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exit_to_kernel_mode(regs);
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}
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static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
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{
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enter_from_kernel_mode(regs);
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local_daif_inherit(regs);
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do_el1_undef(regs, esr);
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local_daif_mask();
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exit_to_kernel_mode(regs);
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}
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static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
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{
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enter_from_kernel_mode(regs);
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local_daif_inherit(regs);
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do_el1_bti(regs, esr);
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local_daif_mask();
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exit_to_kernel_mode(regs);
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}
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static void noinstr el1_dbg(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
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arm64_enter_el1_dbg(regs);
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if (!cortex_a76_erratum_1463225_debug_handler(regs))
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do_debug_exception(far, esr, regs);
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arm64_exit_el1_dbg(regs);
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}
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static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
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{
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enter_from_kernel_mode(regs);
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local_daif_inherit(regs);
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do_el1_fpac(regs, esr);
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local_daif_mask();
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exit_to_kernel_mode(regs);
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}
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asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
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{
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unsigned long esr = read_sysreg(esr_el1);
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switch (ESR_ELx_EC(esr)) {
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case ESR_ELx_EC_DABT_CUR:
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case ESR_ELx_EC_IABT_CUR:
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el1_abort(regs, esr);
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break;
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/*
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* We don't handle ESR_ELx_EC_SP_ALIGN, since we will have hit a
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* recursive exception when trying to push the initial pt_regs.
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*/
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case ESR_ELx_EC_PC_ALIGN:
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el1_pc(regs, esr);
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break;
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case ESR_ELx_EC_SYS64:
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case ESR_ELx_EC_UNKNOWN:
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el1_undef(regs, esr);
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break;
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case ESR_ELx_EC_BTI:
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el1_bti(regs, esr);
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break;
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case ESR_ELx_EC_BREAKPT_CUR:
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case ESR_ELx_EC_SOFTSTP_CUR:
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case ESR_ELx_EC_WATCHPT_CUR:
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case ESR_ELx_EC_BRK64:
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el1_dbg(regs, esr);
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break;
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case ESR_ELx_EC_FPAC:
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el1_fpac(regs, esr);
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break;
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default:
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__panic_unhandled(regs, "64-bit el1h sync", esr);
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}
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}
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static __always_inline void __el1_pnmi(struct pt_regs *regs,
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void (*handler)(struct pt_regs *))
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{
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arm64_enter_nmi(regs);
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do_interrupt_handler(regs, handler);
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arm64_exit_nmi(regs);
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}
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static __always_inline void __el1_irq(struct pt_regs *regs,
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void (*handler)(struct pt_regs *))
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{
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enter_from_kernel_mode(regs);
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irq_enter_rcu();
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do_interrupt_handler(regs, handler);
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irq_exit_rcu();
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arm64_preempt_schedule_irq();
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exit_to_kernel_mode(regs);
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}
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static void noinstr el1_interrupt(struct pt_regs *regs,
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void (*handler)(struct pt_regs *))
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{
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write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
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if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
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__el1_pnmi(regs, handler);
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else
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__el1_irq(regs, handler);
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}
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asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs)
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{
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el1_interrupt(regs, handle_arch_irq);
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}
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asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
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{
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el1_interrupt(regs, handle_arch_fiq);
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}
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asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
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{
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unsigned long esr = read_sysreg(esr_el1);
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local_daif_restore(DAIF_ERRCTX);
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arm64_enter_nmi(regs);
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do_serror(regs, esr);
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arm64_exit_nmi(regs);
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}
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static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
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{
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unsigned long far = read_sysreg(far_el1);
|
|
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_mem_abort(far, esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
unsigned long far = read_sysreg(far_el1);
|
|
|
|
/*
|
|
* We've taken an instruction abort from userspace and not yet
|
|
* re-enabled IRQs. If the address is a kernel address, apply
|
|
* BP hardening prior to enabling IRQs and pre-emption.
|
|
*/
|
|
if (!is_ttbr0_addr(far))
|
|
arm64_apply_bp_hardening();
|
|
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_mem_abort(far, esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_fpsimd_acc(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_sve_acc(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_sme_acc(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_sme_acc(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_fpsimd_exc(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_sys(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
unsigned long far = read_sysreg(far_el1);
|
|
|
|
if (!is_ttbr0_addr(instruction_pointer(regs)))
|
|
arm64_apply_bp_hardening();
|
|
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_sp_pc_abort(far, esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_sp_pc_abort(regs->sp, esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_undef(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_undef(regs, esr);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_bti(struct pt_regs *regs)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_bti(regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_mops(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_mops(regs, esr);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
bad_el0_sync(regs, 0, esr);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_dbg(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
/* Only watchpoints write FAR_EL1, otherwise its UNKNOWN */
|
|
unsigned long far = read_sysreg(far_el1);
|
|
|
|
enter_from_user_mode(regs);
|
|
do_debug_exception(far, esr, regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_svc(struct pt_regs *regs)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
cortex_a76_erratum_1463225_svc_handler();
|
|
do_el0_svc(regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_fpac(regs, esr);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
|
|
{
|
|
unsigned long esr = read_sysreg(esr_el1);
|
|
|
|
switch (ESR_ELx_EC(esr)) {
|
|
case ESR_ELx_EC_SVC64:
|
|
el0_svc(regs);
|
|
break;
|
|
case ESR_ELx_EC_DABT_LOW:
|
|
el0_da(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_IABT_LOW:
|
|
el0_ia(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_FP_ASIMD:
|
|
el0_fpsimd_acc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_SVE:
|
|
el0_sve_acc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_SME:
|
|
el0_sme_acc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_FP_EXC64:
|
|
el0_fpsimd_exc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_SYS64:
|
|
case ESR_ELx_EC_WFx:
|
|
el0_sys(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_SP_ALIGN:
|
|
el0_sp(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_PC_ALIGN:
|
|
el0_pc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_UNKNOWN:
|
|
el0_undef(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_BTI:
|
|
el0_bti(regs);
|
|
break;
|
|
case ESR_ELx_EC_MOPS:
|
|
el0_mops(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_BREAKPT_LOW:
|
|
case ESR_ELx_EC_SOFTSTP_LOW:
|
|
case ESR_ELx_EC_WATCHPT_LOW:
|
|
case ESR_ELx_EC_BRK64:
|
|
el0_dbg(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_FPAC:
|
|
el0_fpac(regs, esr);
|
|
break;
|
|
default:
|
|
el0_inv(regs, esr);
|
|
}
|
|
}
|
|
|
|
static void noinstr el0_interrupt(struct pt_regs *regs,
|
|
void (*handler)(struct pt_regs *))
|
|
{
|
|
enter_from_user_mode(regs);
|
|
|
|
write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
|
|
|
|
if (regs->pc & BIT(55))
|
|
arm64_apply_bp_hardening();
|
|
|
|
irq_enter_rcu();
|
|
do_interrupt_handler(regs, handler);
|
|
irq_exit_rcu();
|
|
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
|
|
{
|
|
el0_interrupt(regs, handle_arch_irq);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_64_irq_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_irq_handler_common(regs);
|
|
}
|
|
|
|
static void noinstr __el0_fiq_handler_common(struct pt_regs *regs)
|
|
{
|
|
el0_interrupt(regs, handle_arch_fiq);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_fiq_handler_common(regs);
|
|
}
|
|
|
|
static void noinstr __el0_error_handler_common(struct pt_regs *regs)
|
|
{
|
|
unsigned long esr = read_sysreg(esr_el1);
|
|
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_ERRCTX);
|
|
arm64_enter_nmi(regs);
|
|
do_serror(regs, esr);
|
|
arm64_exit_nmi(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_error_handler_common(regs);
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
local_daif_restore(DAIF_PROCCTX);
|
|
do_el0_cp15(esr, regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
static void noinstr el0_svc_compat(struct pt_regs *regs)
|
|
{
|
|
enter_from_user_mode(regs);
|
|
cortex_a76_erratum_1463225_svc_handler();
|
|
do_el0_svc_compat(regs);
|
|
exit_to_user_mode(regs);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs)
|
|
{
|
|
unsigned long esr = read_sysreg(esr_el1);
|
|
|
|
switch (ESR_ELx_EC(esr)) {
|
|
case ESR_ELx_EC_SVC32:
|
|
el0_svc_compat(regs);
|
|
break;
|
|
case ESR_ELx_EC_DABT_LOW:
|
|
el0_da(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_IABT_LOW:
|
|
el0_ia(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_FP_ASIMD:
|
|
el0_fpsimd_acc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_FP_EXC32:
|
|
el0_fpsimd_exc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_PC_ALIGN:
|
|
el0_pc(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_UNKNOWN:
|
|
case ESR_ELx_EC_CP14_MR:
|
|
case ESR_ELx_EC_CP14_LS:
|
|
case ESR_ELx_EC_CP14_64:
|
|
el0_undef(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_CP15_32:
|
|
case ESR_ELx_EC_CP15_64:
|
|
el0_cp15(regs, esr);
|
|
break;
|
|
case ESR_ELx_EC_BREAKPT_LOW:
|
|
case ESR_ELx_EC_SOFTSTP_LOW:
|
|
case ESR_ELx_EC_WATCHPT_LOW:
|
|
case ESR_ELx_EC_BKPT32:
|
|
el0_dbg(regs, esr);
|
|
break;
|
|
default:
|
|
el0_inv(regs, esr);
|
|
}
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_32_irq_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_irq_handler_common(regs);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_32_fiq_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_fiq_handler_common(regs);
|
|
}
|
|
|
|
asmlinkage void noinstr el0t_32_error_handler(struct pt_regs *regs)
|
|
{
|
|
__el0_error_handler_common(regs);
|
|
}
|
|
#else /* CONFIG_COMPAT */
|
|
UNHANDLED(el0t, 32, sync)
|
|
UNHANDLED(el0t, 32, irq)
|
|
UNHANDLED(el0t, 32, fiq)
|
|
UNHANDLED(el0t, 32, error)
|
|
#endif /* CONFIG_COMPAT */
|
|
|
|
#ifdef CONFIG_VMAP_STACK
|
|
asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
|
|
{
|
|
unsigned long esr = read_sysreg(esr_el1);
|
|
unsigned long far = read_sysreg(far_el1);
|
|
|
|
arm64_enter_nmi(regs);
|
|
panic_bad_stack(regs, esr, far);
|
|
}
|
|
#endif /* CONFIG_VMAP_STACK */
|
|
|
|
#ifdef CONFIG_ARM_SDE_INTERFACE
|
|
asmlinkage noinstr unsigned long
|
|
__sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
|
|
{
|
|
unsigned long ret;
|
|
|
|
/*
|
|
* We didn't take an exception to get here, so the HW hasn't
|
|
* set/cleared bits in PSTATE that we may rely on.
|
|
*
|
|
* The original SDEI spec (ARM DEN 0054A) can be read ambiguously as to
|
|
* whether PSTATE bits are inherited unchanged or generated from
|
|
* scratch, and the TF-A implementation always clears PAN and always
|
|
* clears UAO. There are no other known implementations.
|
|
*
|
|
* Subsequent revisions (ARM DEN 0054B) follow the usual rules for how
|
|
* PSTATE is modified upon architectural exceptions, and so PAN is
|
|
* either inherited or set per SCTLR_ELx.SPAN, and UAO is always
|
|
* cleared.
|
|
*
|
|
* We must explicitly reset PAN to the expected state, including
|
|
* clearing it when the host isn't using it, in case a VM had it set.
|
|
*/
|
|
if (system_uses_hw_pan())
|
|
set_pstate_pan(1);
|
|
else if (cpu_has_pan())
|
|
set_pstate_pan(0);
|
|
|
|
arm64_enter_nmi(regs);
|
|
ret = do_sdei_event(regs, arg);
|
|
arm64_exit_nmi(regs);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_ARM_SDE_INTERFACE */
|