162 lines
4.0 KiB
C
162 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 - Columbia University and Linaro Ltd.
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* Author: Jintack Lim <jintack.lim@linaro.org>
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*/
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_nested.h>
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#include <asm/sysreg.h>
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#include "sys_regs.h"
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/* Protection against the sysreg repainting madness... */
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#define NV_FTR(r, f) ID_AA64##r##_EL1_##f
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/*
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* Our emulated CPU doesn't support all the possible features. For the
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* sake of simplicity (and probably mental sanity), wipe out a number
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* of feature bits we don't intend to support for the time being.
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* This list should get updated as new features get added to the NV
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* support, and new extension to the architecture.
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*/
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void access_nested_id_reg(struct kvm_vcpu *v, struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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{
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u32 id = reg_to_encoding(r);
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u64 val, tmp;
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val = p->regval;
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switch (id) {
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case SYS_ID_AA64ISAR0_EL1:
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/* Support everything but TME, O.S. and Range TLBIs */
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val &= ~(NV_FTR(ISAR0, TLB) |
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NV_FTR(ISAR0, TME));
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break;
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case SYS_ID_AA64ISAR1_EL1:
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/* Support everything but PtrAuth and Spec Invalidation */
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val &= ~(GENMASK_ULL(63, 56) |
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NV_FTR(ISAR1, SPECRES) |
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NV_FTR(ISAR1, GPI) |
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NV_FTR(ISAR1, GPA) |
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NV_FTR(ISAR1, API) |
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NV_FTR(ISAR1, APA));
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break;
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case SYS_ID_AA64PFR0_EL1:
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/* No AMU, MPAM, S-EL2, RAS or SVE */
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val &= ~(GENMASK_ULL(55, 52) |
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NV_FTR(PFR0, AMU) |
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NV_FTR(PFR0, MPAM) |
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NV_FTR(PFR0, SEL2) |
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NV_FTR(PFR0, RAS) |
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NV_FTR(PFR0, SVE) |
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NV_FTR(PFR0, EL3) |
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NV_FTR(PFR0, EL2) |
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NV_FTR(PFR0, EL1));
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/* 64bit EL1/EL2/EL3 only */
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val |= FIELD_PREP(NV_FTR(PFR0, EL1), 0b0001);
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val |= FIELD_PREP(NV_FTR(PFR0, EL2), 0b0001);
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val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001);
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break;
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case SYS_ID_AA64PFR1_EL1:
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/* Only support SSBS */
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val &= NV_FTR(PFR1, SSBS);
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break;
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case SYS_ID_AA64MMFR0_EL1:
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/* Hide ECV, FGT, ExS, Secure Memory */
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val &= ~(GENMASK_ULL(63, 43) |
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NV_FTR(MMFR0, TGRAN4_2) |
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NV_FTR(MMFR0, TGRAN16_2) |
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NV_FTR(MMFR0, TGRAN64_2) |
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NV_FTR(MMFR0, SNSMEM));
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/* Disallow unsupported S2 page sizes */
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switch (PAGE_SIZE) {
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case SZ_64K:
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val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0001);
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fallthrough;
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case SZ_16K:
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val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0001);
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fallthrough;
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case SZ_4K:
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/* Support everything */
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break;
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}
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/*
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* Since we can't support a guest S2 page size smaller than
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* the host's own page size (due to KVM only populating its
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* own S2 using the kernel's page size), advertise the
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* limitation using FEAT_GTG.
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*/
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switch (PAGE_SIZE) {
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case SZ_4K:
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val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN4_2), 0b0010);
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fallthrough;
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case SZ_16K:
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val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN16_2), 0b0010);
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fallthrough;
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case SZ_64K:
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val |= FIELD_PREP(NV_FTR(MMFR0, TGRAN64_2), 0b0010);
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break;
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}
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/* Cap PARange to 48bits */
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tmp = FIELD_GET(NV_FTR(MMFR0, PARANGE), val);
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if (tmp > 0b0101) {
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val &= ~NV_FTR(MMFR0, PARANGE);
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val |= FIELD_PREP(NV_FTR(MMFR0, PARANGE), 0b0101);
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}
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break;
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case SYS_ID_AA64MMFR1_EL1:
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val &= (NV_FTR(MMFR1, PAN) |
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NV_FTR(MMFR1, LO) |
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NV_FTR(MMFR1, HPDS) |
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NV_FTR(MMFR1, VH) |
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NV_FTR(MMFR1, VMIDBits));
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break;
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case SYS_ID_AA64MMFR2_EL1:
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val &= ~(NV_FTR(MMFR2, EVT) |
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NV_FTR(MMFR2, BBM) |
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NV_FTR(MMFR2, TTL) |
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GENMASK_ULL(47, 44) |
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NV_FTR(MMFR2, ST) |
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NV_FTR(MMFR2, CCIDX) |
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NV_FTR(MMFR2, VARange));
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/* Force TTL support */
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val |= FIELD_PREP(NV_FTR(MMFR2, TTL), 0b0001);
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break;
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case SYS_ID_AA64DFR0_EL1:
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/* Only limited support for PMU, Debug, BPs and WPs */
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val &= (NV_FTR(DFR0, PMUVer) |
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NV_FTR(DFR0, WRPs) |
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NV_FTR(DFR0, BRPs) |
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NV_FTR(DFR0, DebugVer));
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/* Cap Debug to ARMv8.1 */
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tmp = FIELD_GET(NV_FTR(DFR0, DebugVer), val);
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if (tmp > 0b0111) {
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val &= ~NV_FTR(DFR0, DebugVer);
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val |= FIELD_PREP(NV_FTR(DFR0, DebugVer), 0b0111);
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}
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break;
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default:
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/* Unknown register, just wipe it clean */
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val = 0;
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break;
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}
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p->regval = val;
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}
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