89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_BARRIER_H
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#define __ASM_CSKY_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() asm volatile ("nop\n":::"memory")
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#ifdef CONFIG_SMP
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/*
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* bar.brwarws: ordering barrier for all load/store instructions
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* before/after
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*
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* |31|30 26|25 21|20 16|15 10|9 5|4 0|
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* 1 10000 00000 00000 100001 00001 0 bw br aw ar
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*
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* b: before
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* a: after
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* r: read
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* w: write
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*
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* Here are all combinations:
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*
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* bar.brw
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* bar.br
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* bar.bw
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* bar.arw
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* bar.ar
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* bar.aw
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* bar.brwarw
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* bar.brarw
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* bar.bwarw
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* bar.brwar
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* bar.brwaw
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* bar.brar
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* bar.bwaw
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*/
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#define FULL_FENCE ".long 0x842fc000\n"
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#define ACQUIRE_FENCE ".long 0x8427c000\n"
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#define RELEASE_FENCE ".long 0x842ec000\n"
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#define __bar_brw() asm volatile (".long 0x842cc000\n":::"memory")
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#define __bar_br() asm volatile (".long 0x8424c000\n":::"memory")
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#define __bar_bw() asm volatile (".long 0x8428c000\n":::"memory")
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#define __bar_arw() asm volatile (".long 0x8423c000\n":::"memory")
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#define __bar_ar() asm volatile (".long 0x8421c000\n":::"memory")
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#define __bar_aw() asm volatile (".long 0x8422c000\n":::"memory")
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#define __bar_brwarw() asm volatile (FULL_FENCE:::"memory")
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#define __bar_brarw() asm volatile (ACQUIRE_FENCE:::"memory")
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#define __bar_bwarw() asm volatile (".long 0x842bc000\n":::"memory")
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#define __bar_brwar() asm volatile (".long 0x842dc000\n":::"memory")
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#define __bar_brwaw() asm volatile (RELEASE_FENCE:::"memory")
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#define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory")
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#define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory")
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#define __bar_bwaw() asm volatile (".long 0x842ac000\n":::"memory")
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#define __smp_mb() __bar_brwarw()
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#define __smp_rmb() __bar_brar()
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#define __smp_wmb() __bar_bwaw()
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#define __smp_acquire_fence() __bar_brarw()
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#define __smp_release_fence() __bar_brwaw()
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#endif /* CONFIG_SMP */
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/*
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* sync: completion barrier, all sync.xx instructions
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* guarantee the last response received by bus transaction
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* made by ld/st instructions before sync.s
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* sync.s: inherit from sync, but also shareable to other cores
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* sync.i: inherit from sync, but also flush cpu pipeline
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* sync.is: the same with sync.i + sync.s
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*/
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#define mb() asm volatile ("sync\n":::"memory")
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#ifdef CONFIG_CPU_HAS_CACHEV2
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/*
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* Using three sync.is to prevent speculative PTW
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*/
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#define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory")
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_CSKY_BARRIER_H */
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