556 lines
17 KiB
C
556 lines
17 KiB
C
/*
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* XHCI HCD glue for Cavium Octeon III SOCs.
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*
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* Copyright (C) 2010-2017 Cavium Networks
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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/*
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* USB Control Register
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*/
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#define USBDRD_UCTL_CTL 0x00
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/* BIST fast-clear mode select. A BIST run with this bit set
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* clears all entries in USBH RAMs to 0x0.
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*/
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# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63)
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/* 1 = Start BIST and cleared by hardware */
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# define USBDRD_UCTL_CTL_START_BIST BIT(62)
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/* Reference clock select for SuperSpeed and HighSpeed PLLs:
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* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
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* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
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* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60)
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/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
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# define USBDRD_UCTL_CTL_SSC_EN BIT(59)
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/* Spread-spectrum clock modulation range:
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* 0x0 = -4980 ppm downspread
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* 0x1 = -4492 ppm downspread
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* 0x2 = -4003 ppm downspread
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* 0x3 - 0x7 = Reserved
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*/
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# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56)
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/* Enable non-standard oscillator frequencies:
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* [55:53] = modules -1
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* [52:47] = 2's complement push amount, 0 = Feature disabled
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*/
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# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47)
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/* Reference clock multiplier for non-standard frequencies:
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* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* Other Values = Reserved
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*/
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# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40)
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/* Enable reference clock to prescaler for SuperSpeed functionality.
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* Should always be set to "1"
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*/
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# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39)
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/* Divide the reference clock by 2 before entering the
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* REF_CLK_FSEL divider:
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* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
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* If REF_CLK_SEL = 0x2 or 0x3, then:
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* 0x1 = DLMC_REF_CLK* is 125MHz
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* 0x0 = DLMC_REF_CLK* is another supported frequency
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38)
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/* Select reference clock freqnuency for both PLL blocks:
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* 0x27 = REF_CLK_SEL is 0x0 or 0x1
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* 0x07 = REF_CLK_SEL is 0x2 or 0x3
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32)
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/* Controller clock enable. */
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# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30)
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/* Select bypass input to controller clock divider:
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* 0x0 = Use divided coprocessor clock from H_CLKDIV
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* 0x1 = Use clock from GPIO pins
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*/
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# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29)
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/* Reset controller clock divider. */
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# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28)
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/* Clock divider select:
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* 0x0 = divide by 1
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* 0x1 = divide by 2
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* 0x2 = divide by 4
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* 0x3 = divide by 6
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* 0x4 = divide by 8
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* 0x5 = divide by 16
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* 0x6 = divide by 24
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* 0x7 = divide by 32
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*/
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# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24)
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/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21)
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/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20)
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/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18)
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/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16)
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/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14)
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/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12)
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/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4)
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/* Controller mode: 0x0 = Host, 0x1 = Device */
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# define USBDRD_UCTL_CTL_DRD_MODE BIT(3)
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/* PHY reset */
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# define USBDRD_UCTL_CTL_UPHY_RST BIT(2)
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/* Software reset UAHC */
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# define USBDRD_UCTL_CTL_UAHC_RST BIT(1)
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/* Software resets UCTL */
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# define USBDRD_UCTL_CTL_UCTL_RST BIT(0)
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#define USBDRD_UCTL_BIST_STATUS 0x08
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#define USBDRD_UCTL_SPARE0 0x10
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#define USBDRD_UCTL_INTSTAT 0x30
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#define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port))
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#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port))
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/*
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* UCTL Configuration Register
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*/
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#define USBDRD_UCTL_HOST_CFG 0xe0
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/* Indicates minimum value of all received BELT values */
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# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48)
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/* HS jitter adjustment */
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# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32)
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/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
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# define USBDRD_UCTL_HOST_CFG_BME BIT(28)
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/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
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# define USBDRD_UCTL_HOST_OCI_EN BIT(27)
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/* Overcurrent sene selection:
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* 0x0 = Overcurrent indication from off-chip is active-low
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* 0x1 = Overcurrent indication from off-chip is active-high
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*/
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# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26)
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/* Port power control enable: 0x0 = unavailable, 0x1 = available */
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# define USBDRD_UCTL_HOST_PPC_EN BIT(25)
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/* Port power control sense selection:
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* 0x0 = Port power to off-chip is active-low
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* 0x1 = Port power to off-chip is active-high
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*/
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# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24)
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/*
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* UCTL Shim Features Register
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*/
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#define USBDRD_UCTL_SHIM_CFG 0xe8
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/* Out-of-bound UAHC register access: 0 = read, 1 = write */
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# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63)
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/* SRCID error log for out-of-bound UAHC register access:
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* [59:58] = chipID
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* [57] = Request source: 0 = core, 1 = NCB-device
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* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
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* [50:48] = SubID
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*/
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# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48)
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/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
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# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47)
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/* Encoded error type for bad UAHC DMA */
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# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40)
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/* Select the IOI read command used by DMA accesses */
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# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12)
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/* Select endian format for DMA accesses to the L2C:
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* 0x0 = Little endian
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* 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
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# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8)
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/* Select endian format for IOI CSR access to UAHC:
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* 0x0 = Little endian
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* 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
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# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0)
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8
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static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
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{
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return cvmx_readq_csr(addr);
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}
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static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val)
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{
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cvmx_writeq_csr(base, val);
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}
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static void dwc3_octeon_config_gpio(int index, int gpio)
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{
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union cvmx_gpio_bit_cfgx gpio_bit;
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if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
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OCTEON_IS_MODEL(OCTEON_CNF75XX))
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&& gpio <= 31) {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
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} else if (gpio <= 15) {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
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} else {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
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cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
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}
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}
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#else
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static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
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{
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return 0;
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}
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static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }
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static inline void dwc3_octeon_config_gpio(int index, int gpio) { }
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#endif
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static int dwc3_octeon_get_divider(void)
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{
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static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 };
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int div = 0;
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while (div < ARRAY_SIZE(clk_div)) {
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uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
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if (rate <= 300000000 && rate >= 150000000)
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return div;
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div++;
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}
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return -EINVAL;
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}
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static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
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{
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uint32_t gpio_pwr[3];
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int gpio, len, power_active_low;
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struct device_node *node = dev->of_node;
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u64 val;
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void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
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if (of_find_property(node, "power", &len) != NULL) {
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if (len == 12) {
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of_property_read_u32_array(node, "power", gpio_pwr, 3);
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power_active_low = gpio_pwr[2] & 0x01;
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gpio = gpio_pwr[1];
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} else if (len == 8) {
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of_property_read_u32_array(node, "power", gpio_pwr, 2);
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power_active_low = 0;
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gpio = gpio_pwr[1];
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} else {
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dev_err(dev, "invalid power configuration\n");
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return -EINVAL;
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}
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dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio);
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/* Enable XHCI power control and set if active high or low. */
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val = dwc3_octeon_readq(uctl_host_cfg_reg);
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val |= USBDRD_UCTL_HOST_PPC_EN;
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if (power_active_low)
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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else
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val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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dwc3_octeon_writeq(uctl_host_cfg_reg, val);
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} else {
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/* Disable XHCI power control and set if active high. */
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val = dwc3_octeon_readq(uctl_host_cfg_reg);
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val &= ~USBDRD_UCTL_HOST_PPC_EN;
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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dwc3_octeon_writeq(uctl_host_cfg_reg, val);
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dev_info(dev, "power control disabled\n");
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}
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return 0;
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}
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static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
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{
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int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
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u32 clock_rate;
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u64 val;
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void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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if (dev->of_node) {
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const char *ss_clock_type;
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const char *hs_clock_type;
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i = of_property_read_u32(dev->of_node,
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"refclk-frequency", &clock_rate);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-ss", &ss_clock_type);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-hs", &hs_clock_type);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
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ref_clk_sel = 0;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 2;
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else
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
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ref_clk_sel = 1;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 3;
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else {
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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ref_clk_sel = 3;
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}
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} else
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dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
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(clock_rate != 100000000))
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dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n",
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clock_rate);
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} else {
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dev_err(dev, "No USB UCTL device node\n");
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return -EINVAL;
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}
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/*
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* Step 1: Wait for all voltages to be stable...that surely
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* happened before starting the kernel. SKIP
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*/
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/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
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/* Step 3: Assert all resets. */
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_UPHY_RST |
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USBDRD_UCTL_CTL_UAHC_RST |
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USBDRD_UCTL_CTL_UCTL_RST;
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 4a: Reset the clock dividers. */
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_H_CLKDIV_RST;
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 4b: Select controller clock frequency. */
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div = dwc3_octeon_get_divider();
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if (div < 0) {
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dev_err(dev, "clock divider invalid\n");
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return div;
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}
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
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val |= USBDRD_UCTL_CTL_H_CLK_EN;
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
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(!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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return -EINVAL;
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}
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/* Step 4c: Deassert the controller clock divider reset. */
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST;
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 5a: Reference clock configuration. */
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2;
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val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
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ref_clk_fsel = 0x07;
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switch (clock_rate) {
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|
default:
|
|
dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
|
|
clock_rate);
|
|
fallthrough;
|
|
case 100000000:
|
|
mpll_mul = 0x19;
|
|
if (ref_clk_sel < 2)
|
|
ref_clk_fsel = 0x27;
|
|
break;
|
|
case 50000000:
|
|
mpll_mul = 0x32;
|
|
break;
|
|
case 125000000:
|
|
mpll_mul = 0x28;
|
|
break;
|
|
}
|
|
val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
|
|
val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
|
|
|
|
val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER;
|
|
val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
|
|
|
|
/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
|
|
val |= USBDRD_UCTL_CTL_SSC_EN;
|
|
|
|
/* Step 5c: Enable SuperSpeed. */
|
|
val |= USBDRD_UCTL_CTL_REF_SSP_EN;
|
|
|
|
/* Step 5d: Configure PHYs. SKIP */
|
|
|
|
/* Step 6a & 6b: Power up PHYs. */
|
|
val |= USBDRD_UCTL_CTL_HS_POWER_EN;
|
|
val |= USBDRD_UCTL_CTL_SS_POWER_EN;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
|
|
/* Step 7: Wait 10 controller-clock cycles to take effect. */
|
|
udelay(10);
|
|
|
|
/* Step 8a: Deassert UCTL reset signal. */
|
|
val = dwc3_octeon_readq(uctl_ctl_reg);
|
|
val &= ~USBDRD_UCTL_CTL_UCTL_RST;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
|
|
/* Step 8b: Wait 10 controller-clock cycles. */
|
|
udelay(10);
|
|
|
|
/* Steo 8c: Setup power-power control. */
|
|
if (dwc3_octeon_config_power(dev, base))
|
|
return -EINVAL;
|
|
|
|
/* Step 8d: Deassert UAHC reset signal. */
|
|
val = dwc3_octeon_readq(uctl_ctl_reg);
|
|
val &= ~USBDRD_UCTL_CTL_UAHC_RST;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
|
|
/* Step 8e: Wait 10 controller-clock cycles. */
|
|
udelay(10);
|
|
|
|
/* Step 9: Enable conditional coprocessor clock of UCTL. */
|
|
val = dwc3_octeon_readq(uctl_ctl_reg);
|
|
val |= USBDRD_UCTL_CTL_CSCLK_EN;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
|
|
/*Step 10: Set for host mode only. */
|
|
val = dwc3_octeon_readq(uctl_ctl_reg);
|
|
val &= ~USBDRD_UCTL_CTL_DRD_MODE;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init dwc3_octeon_set_endian_mode(void __iomem *base)
|
|
{
|
|
u64 val;
|
|
void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG;
|
|
|
|
val = dwc3_octeon_readq(uctl_shim_cfg_reg);
|
|
val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
|
|
val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
|
|
#ifdef __BIG_ENDIAN
|
|
val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
|
|
val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
|
|
#endif
|
|
dwc3_octeon_writeq(uctl_shim_cfg_reg, val);
|
|
}
|
|
|
|
static void __init dwc3_octeon_phy_reset(void __iomem *base)
|
|
{
|
|
u64 val;
|
|
void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
|
|
|
|
val = dwc3_octeon_readq(uctl_ctl_reg);
|
|
val &= ~USBDRD_UCTL_CTL_UPHY_RST;
|
|
dwc3_octeon_writeq(uctl_ctl_reg, val);
|
|
}
|
|
|
|
static int __init dwc3_octeon_device_init(void)
|
|
{
|
|
const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
|
|
struct platform_device *pdev;
|
|
struct device_node *node;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
|
|
/*
|
|
* There should only be three universal controllers, "uctl"
|
|
* in the device tree. Two USB and a SATA, which we ignore.
|
|
*/
|
|
node = NULL;
|
|
do {
|
|
node = of_find_node_by_name(node, "uctl");
|
|
if (!node)
|
|
return -ENODEV;
|
|
|
|
if (of_device_is_compatible(node, compat_node_name)) {
|
|
pdev = of_find_device_by_node(node);
|
|
if (!pdev)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* The code below maps in the registers necessary for
|
|
* setting up the clocks and reseting PHYs. We must
|
|
* release the resources so the dwc3 subsystem doesn't
|
|
* know the difference.
|
|
*/
|
|
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
|
if (IS_ERR(base)) {
|
|
put_device(&pdev->dev);
|
|
return PTR_ERR(base);
|
|
}
|
|
|
|
mutex_lock(&dwc3_octeon_clocks_mutex);
|
|
if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0)
|
|
dev_info(&pdev->dev, "clocks initialized.\n");
|
|
dwc3_octeon_set_endian_mode(base);
|
|
dwc3_octeon_phy_reset(base);
|
|
mutex_unlock(&dwc3_octeon_clocks_mutex);
|
|
devm_iounmap(&pdev->dev, base);
|
|
devm_release_mem_region(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
put_device(&pdev->dev);
|
|
}
|
|
} while (node != NULL);
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(dwc3_octeon_device_init);
|
|
|
|
MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("USB driver for OCTEON III SoC");
|