143 lines
7.3 KiB
C
143 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MMU_MASKS_H_
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#define ASIC_REG_MMU_MASKS_H_
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/*
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*****************************************
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* MMU (Prototype: MMU)
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*****************************************
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*/
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/* MMU_INPUT_FIFO_THRESHOLD */
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#define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
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#define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
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#define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 4
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#define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
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#define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 8
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#define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
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#define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 12
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#define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
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#define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 16
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#define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
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#define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 20
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#define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
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#define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 24
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#define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
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/* MMU_MMU_ENABLE */
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#define MMU_MMU_ENABLE_R_SHIFT 0
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#define MMU_MMU_ENABLE_R_MASK 0x1
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/* MMU_FORCE_ORDERING */
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#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0
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#define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1
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#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 1
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#define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2
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#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 2
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#define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4
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#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 3
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#define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8
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#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 4
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#define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10
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#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 5
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#define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20
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#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 6
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#define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40
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#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 8
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#define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100
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#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 9
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#define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200
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#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 10
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#define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400
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#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 11
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#define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800
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#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 12
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#define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000
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#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 13
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#define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000
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#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 14
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#define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000
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/* MMU_FEATURE_ENABLE */
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#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
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#define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
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#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1
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#define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
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#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2
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#define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
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#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3
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#define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
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#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4
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#define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10
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#define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5
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#define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20
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/* MMU_VA_ORDERING_MASK_31_7 */
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#define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0
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#define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF
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/* MMU_VA_ORDERING_MASK_49_32 */
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#define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0
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#define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF
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/* MMU_LOG2_DDR_SIZE */
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#define MMU_LOG2_DDR_SIZE_R_SHIFT 0
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#define MMU_LOG2_DDR_SIZE_R_MASK 0xFF
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/* MMU_SCRAMBLER */
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#define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0
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#define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F
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#define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6
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#define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40
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#define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7
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#define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80
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/* MMU_MEM_INIT_BUSY */
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#define MMU_MEM_INIT_BUSY_DATA_SHIFT 0
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#define MMU_MEM_INIT_BUSY_DATA_MASK 0x3
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#define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2
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#define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4
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#define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3
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#define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8
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/* MMU_SPI_MASK */
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#define MMU_SPI_MASK_R_SHIFT 0
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#define MMU_SPI_MASK_R_MASK 0xFF
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/* MMU_SPI_CAUSE */
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#define MMU_SPI_CAUSE_R_SHIFT 0
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#define MMU_SPI_CAUSE_R_MASK 0xFF
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/* MMU_PAGE_ERROR_CAPTURE */
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#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0
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#define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
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#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18
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#define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
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/* MMU_PAGE_ERROR_CAPTURE_VA */
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#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
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#define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
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/* MMU_ACCESS_ERROR_CAPTURE */
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#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0
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#define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
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#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18
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#define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
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/* MMU_ACCESS_ERROR_CAPTURE_VA */
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#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
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#define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF
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#endif /* ASIC_REG_MMU_MASKS_H_ */
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