114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Amlogic A1 Peripherals Clock Controller internals
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*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
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*/
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#ifndef __A1_PERIPHERALS_H
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#define __A1_PERIPHERALS_H
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/* peripherals clock controller register offset */
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#define SYS_OSCIN_CTRL 0x0
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#define RTC_BY_OSCIN_CTRL0 0x4
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#define RTC_BY_OSCIN_CTRL1 0x8
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#define RTC_CTRL 0xc
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#define SYS_CLK_CTRL0 0x10
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#define SYS_CLK_EN0 0x1c
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#define SYS_CLK_EN1 0x20
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#define AXI_CLK_EN 0x24
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#define DSPA_CLK_EN 0x28
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#define DSPB_CLK_EN 0x2c
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#define DSPA_CLK_CTRL0 0x30
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#define DSPB_CLK_CTRL0 0x34
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#define CLK12_24_CTRL 0x38
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#define GEN_CLK_CTRL 0x3c
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#define SAR_ADC_CLK_CTRL 0xc0
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#define PWM_CLK_AB_CTRL 0xc4
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#define PWM_CLK_CD_CTRL 0xc8
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#define PWM_CLK_EF_CTRL 0xcc
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#define SPICC_CLK_CTRL 0xd0
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#define TS_CLK_CTRL 0xd4
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#define SPIFC_CLK_CTRL 0xd8
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#define USB_BUSCLK_CTRL 0xdc
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#define SD_EMMC_CLK_CTRL 0xe0
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#define CECA_CLK_CTRL0 0xe4
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#define CECA_CLK_CTRL1 0xe8
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#define CECB_CLK_CTRL0 0xec
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#define CECB_CLK_CTRL1 0xf0
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#define PSRAM_CLK_CTRL 0xf4
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#define DMC_CLK_CTRL 0xf8
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
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/*
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* CLKID index values for internal clocks
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/a1-peripherals-clkc.h.
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* Only the clocks ids we don't want to expose, such as the internal muxes and
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* dividers of composite clocks, will remain defined here.
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*/
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#define CLKID_XTAL_IN 0
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#define CLKID_DSPA_SEL 61
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#define CLKID_DSPB_SEL 62
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#define CLKID_SARADC_SEL 74
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#define CLKID_SYS_A_SEL 89
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#define CLKID_SYS_A_DIV 90
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#define CLKID_SYS_A 91
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#define CLKID_SYS_B_SEL 92
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#define CLKID_SYS_B_DIV 93
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#define CLKID_SYS_B 94
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#define CLKID_DSPA_A_DIV 96
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#define CLKID_DSPA_A 97
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#define CLKID_DSPA_B_DIV 99
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#define CLKID_DSPA_B 100
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#define CLKID_DSPB_A_DIV 102
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#define CLKID_DSPB_A 103
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#define CLKID_DSPB_B_DIV 105
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#define CLKID_DSPB_B 106
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#define CLKID_RTC_32K_IN 107
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#define CLKID_RTC_32K_DIV 108
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#define CLKID_RTC_32K_XTAL 109
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#define CLKID_RTC_32K_SEL 110
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#define CLKID_CECB_32K_IN 111
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#define CLKID_CECB_32K_DIV 112
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#define CLKID_CECA_32K_IN 115
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#define CLKID_CECA_32K_DIV 116
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#define CLKID_DIV2_PRE 119
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#define CLKID_24M_DIV2 120
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#define CLKID_GEN_DIV 122
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#define CLKID_SARADC_DIV 123
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#define CLKID_PWM_A_DIV 125
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#define CLKID_PWM_B_DIV 127
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#define CLKID_PWM_C_DIV 129
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#define CLKID_PWM_D_DIV 131
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#define CLKID_PWM_E_DIV 133
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#define CLKID_PWM_F_DIV 135
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#define CLKID_SPICC_SEL 136
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#define CLKID_SPICC_DIV 137
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#define CLKID_SPICC_SEL2 138
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#define CLKID_TS_DIV 139
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#define CLKID_SPIFC_SEL 140
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#define CLKID_SPIFC_DIV 141
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#define CLKID_SPIFC_SEL2 142
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#define CLKID_USB_BUS_SEL 143
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#define CLKID_USB_BUS_DIV 144
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#define CLKID_SD_EMMC_SEL 145
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#define CLKID_SD_EMMC_DIV 146
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#define CLKID_PSRAM_SEL 148
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#define CLKID_PSRAM_DIV 149
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#define CLKID_PSRAM_SEL2 150
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#define CLKID_DMC_SEL 151
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#define CLKID_DMC_DIV 152
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#define CLKID_DMC_SEL2 153
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#define NR_CLKS 154
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#endif /* __A1_PERIPHERALS_H */
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