257 lines
7.0 KiB
C
257 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016 Maxime Ripard. All rights reserved.
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*/
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#ifndef _CCU_DIV_H_
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#define _CCU_DIV_H_
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#include <linux/clk-provider.h>
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#include "ccu_common.h"
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#include "ccu_mux.h"
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/**
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* struct ccu_div_internal - Internal divider description
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* @shift: Bit offset of the divider in its register
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* @width: Width of the divider field in its register
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* @max: Maximum value allowed for that divider. This is the
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* arithmetic value, not the maximum value to be set in the
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* register.
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* @flags: clk_divider flags to apply on this divider
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* @table: Divider table pointer (if applicable)
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*
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* That structure represents a single divider, and is meant to be
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* embedded in other structures representing the various clock
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* classes.
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*
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* It is basically a wrapper around the clk_divider functions
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* arguments.
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*/
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struct ccu_div_internal {
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u8 shift;
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u8 width;
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u32 max;
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u32 offset;
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u32 flags;
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struct clk_div_table *table;
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};
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#define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \
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{ \
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.shift = _shift, \
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.width = _width, \
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.flags = _flags, \
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.table = _table, \
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}
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#define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
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_SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
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#define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \
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{ \
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.shift = _shift, \
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.width = _width, \
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.flags = _flags, \
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.max = _max, \
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.offset = _off, \
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}
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#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
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_SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
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#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
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_SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
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#define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \
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_SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
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#define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \
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_SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _offset, 0, 0)
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#define _SUNXI_CCU_DIV(_shift, _width) \
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_SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
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struct ccu_div {
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u32 enable;
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struct ccu_div_internal div;
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struct ccu_mux_internal mux;
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struct ccu_common common;
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unsigned int fixed_post_div;
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};
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#define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
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_shift, _width, \
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_table, _gate, _flags) \
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struct ccu_div _struct = { \
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.div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
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_table), \
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.enable = _gate, \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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} \
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}
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#define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
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_shift, _width, \
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_table, _flags) \
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SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
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_shift, _width, _table, 0, \
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_flags)
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#define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \
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_shift, _width, \
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_table, _flags) \
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struct ccu_div _struct = { \
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.div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
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_table), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_HW(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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} \
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}
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#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_parents, _table, \
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_reg, \
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_mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_gate, _flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parents, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_gate, _flags) \
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SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_parents, NULL, \
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_reg, _mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_gate, _flags)
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#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_flags) \
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SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_parents, NULL, \
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_reg, _mshift, _mwidth, \
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_muxshift, _muxwidth, \
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0, _flags)
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#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, _gate, \
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_flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \
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_flags) \
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SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, 0, _flags)
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#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_gate, _flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
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_parents, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_flags) \
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SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, \
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_muxshift, _muxwidth, \
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0, _flags)
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#define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_gate, _flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
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_parents, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, _gate, \
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_flags) \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_HWS(_name, \
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_parent, \
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&ccu_div_ops, \
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_flags), \
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}, \
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}
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#define SUNXI_CCU_M_HWS(_struct, _name, _parent, _reg, _mshift, \
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_mwidth, _flags) \
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SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
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_mshift, _mwidth, 0, _flags)
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static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
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{
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struct ccu_common *common = hw_to_ccu_common(hw);
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return container_of(common, struct ccu_div, common);
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}
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extern const struct clk_ops ccu_div_ops;
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#endif /* _CCU_DIV_H_ */
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