674 lines
16 KiB
C
674 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AMD Cryptographic Coprocessor (CCP) driver
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*
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* Copyright (C) 2013,2017 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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* Author: Gary R Hook <gary.hook@amd.com>
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*/
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#ifndef __CCP_DEV_H__
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#define __CCP_DEV_H__
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/wait.h>
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#include <linux/dma-direction.h>
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#include <linux/dmapool.h>
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#include <linux/hw_random.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/dmaengine.h>
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#include "sp-dev.h"
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#define MAX_CCP_NAME_LEN 16
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#define MAX_DMAPOOL_NAME_LEN 32
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#define MAX_HW_QUEUES 5
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#define MAX_CMD_QLEN 100
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#define TRNG_RETRIES 10
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#define CACHE_NONE 0x00
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#define CACHE_WB_NO_ALLOC 0xb7
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/****** Register Mappings ******/
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#define Q_MASK_REG 0x000
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#define TRNG_OUT_REG 0x00c
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#define IRQ_MASK_REG 0x040
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#define IRQ_STATUS_REG 0x200
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#define DEL_CMD_Q_JOB 0x124
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#define DEL_Q_ACTIVE 0x00000200
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#define DEL_Q_ID_SHIFT 6
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#define CMD_REQ0 0x180
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#define CMD_REQ_INCR 0x04
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#define CMD_Q_STATUS_BASE 0x210
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#define CMD_Q_INT_STATUS_BASE 0x214
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#define CMD_Q_STATUS_INCR 0x20
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#define CMD_Q_CACHE_BASE 0x228
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#define CMD_Q_CACHE_INC 0x20
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#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
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#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
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/* ------------------------ CCP Version 5 Specifics ------------------------ */
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#define CMD5_QUEUE_MASK_OFFSET 0x00
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#define CMD5_QUEUE_PRIO_OFFSET 0x04
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#define CMD5_REQID_CONFIG_OFFSET 0x08
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#define CMD5_CMD_TIMEOUT_OFFSET 0x10
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#define LSB_PUBLIC_MASK_LO_OFFSET 0x18
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#define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
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#define LSB_PRIVATE_MASK_LO_OFFSET 0x20
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#define LSB_PRIVATE_MASK_HI_OFFSET 0x24
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#define CMD5_PSP_CCP_VERSION 0x100
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#define CMD5_Q_CONTROL_BASE 0x0000
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#define CMD5_Q_TAIL_LO_BASE 0x0004
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#define CMD5_Q_HEAD_LO_BASE 0x0008
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#define CMD5_Q_INT_ENABLE_BASE 0x000C
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#define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
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#define CMD5_Q_STATUS_BASE 0x0100
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#define CMD5_Q_INT_STATUS_BASE 0x0104
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#define CMD5_Q_DMA_STATUS_BASE 0x0108
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#define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
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#define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
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#define CMD5_Q_ABORT_BASE 0x0114
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#define CMD5_Q_AX_CACHE_BASE 0x0118
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#define CMD5_CONFIG_0_OFFSET 0x6000
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#define CMD5_TRNG_CTL_OFFSET 0x6008
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#define CMD5_AES_MASK_OFFSET 0x6010
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#define CMD5_CLK_GATE_CTL_OFFSET 0x603C
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/* Address offset between two virtual queue registers */
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#define CMD5_Q_STATUS_INCR 0x1000
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/* Bit masks */
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#define CMD5_Q_RUN 0x1
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#define CMD5_Q_HALT 0x2
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#define CMD5_Q_MEM_LOCATION 0x4
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#define CMD5_Q_SIZE 0x1F
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#define CMD5_Q_SHIFT 3
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#define COMMANDS_PER_QUEUE 16
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#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
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CMD5_Q_SIZE)
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#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
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#define Q_DESC_SIZE sizeof(struct ccp5_desc)
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#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
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#define INT_COMPLETION 0x1
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#define INT_ERROR 0x2
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#define INT_QUEUE_STOPPED 0x4
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#define INT_EMPTY_QUEUE 0x8
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#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
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#define LSB_REGION_WIDTH 5
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#define MAX_LSB_CNT 8
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#define LSB_SIZE 16
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#define LSB_ITEM_SIZE 32
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#define PLSB_MAP_SIZE (LSB_SIZE)
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#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
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#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
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/* ------------------------ CCP Version 3 Specifics ------------------------ */
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#define REQ0_WAIT_FOR_WRITE 0x00000004
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#define REQ0_INT_ON_COMPLETE 0x00000002
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#define REQ0_STOP_ON_COMPLETE 0x00000001
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#define REQ0_CMD_Q_SHIFT 9
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#define REQ0_JOBID_SHIFT 3
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/****** REQ1 Related Values ******/
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#define REQ1_PROTECT_SHIFT 27
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#define REQ1_ENGINE_SHIFT 23
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#define REQ1_KEY_KSB_SHIFT 2
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#define REQ1_EOM 0x00000002
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#define REQ1_INIT 0x00000001
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/* AES Related Values */
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#define REQ1_AES_TYPE_SHIFT 21
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#define REQ1_AES_MODE_SHIFT 18
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#define REQ1_AES_ACTION_SHIFT 17
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#define REQ1_AES_CFB_SIZE_SHIFT 10
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/* XTS-AES Related Values */
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#define REQ1_XTS_AES_SIZE_SHIFT 10
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/* SHA Related Values */
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#define REQ1_SHA_TYPE_SHIFT 21
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/* RSA Related Values */
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#define REQ1_RSA_MOD_SIZE_SHIFT 10
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/* Pass-Through Related Values */
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#define REQ1_PT_BW_SHIFT 12
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#define REQ1_PT_BS_SHIFT 10
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/* ECC Related Values */
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#define REQ1_ECC_AFFINE_CONVERT 0x00200000
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#define REQ1_ECC_FUNCTION_SHIFT 18
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/****** REQ4 Related Values ******/
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#define REQ4_KSB_SHIFT 18
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#define REQ4_MEMTYPE_SHIFT 16
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/****** REQ6 Related Values ******/
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#define REQ6_MEMTYPE_SHIFT 16
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/****** Key Storage Block ******/
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#define KSB_START 77
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#define KSB_END 127
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#define KSB_COUNT (KSB_END - KSB_START + 1)
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#define CCP_SB_BITS 256
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#define CCP_JOBID_MASK 0x0000003f
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/* ------------------------ General CCP Defines ------------------------ */
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#define CCP_DMA_DFLT 0x0
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#define CCP_DMA_PRIV 0x1
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#define CCP_DMA_PUB 0x2
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#define CCP_DMAPOOL_MAX_SIZE 64
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#define CCP_DMAPOOL_ALIGN BIT(5)
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#define CCP_REVERSE_BUF_SIZE 64
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#define CCP_AES_KEY_SB_COUNT 1
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#define CCP_AES_CTX_SB_COUNT 1
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#define CCP_XTS_AES_KEY_SB_COUNT 1
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#define CCP5_XTS_AES_KEY_SB_COUNT 2
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#define CCP_XTS_AES_CTX_SB_COUNT 1
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#define CCP_DES3_KEY_SB_COUNT 1
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#define CCP_DES3_CTX_SB_COUNT 1
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#define CCP_SHA_SB_COUNT 1
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#define CCP_RSA_MAX_WIDTH 4096
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#define CCP5_RSA_MAX_WIDTH 16384
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#define CCP_PASSTHRU_BLOCKSIZE 256
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#define CCP_PASSTHRU_MASKSIZE 32
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#define CCP_PASSTHRU_SB_COUNT 1
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#define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
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#define CCP_ECC_MAX_OPERANDS 6
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#define CCP_ECC_MAX_OUTPUTS 3
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#define CCP_ECC_SRC_BUF_SIZE 448
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#define CCP_ECC_DST_BUF_SIZE 192
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#define CCP_ECC_OPERAND_SIZE 64
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#define CCP_ECC_OUTPUT_SIZE 64
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#define CCP_ECC_RESULT_OFFSET 60
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#define CCP_ECC_RESULT_SUCCESS 0x0001
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#define CCP_SB_BYTES 32
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struct ccp_op;
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struct ccp_device;
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struct ccp_cmd;
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struct ccp_fns;
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struct ccp_dma_cmd {
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struct list_head entry;
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struct ccp_cmd ccp_cmd;
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};
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struct ccp_dma_desc {
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struct list_head entry;
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struct ccp_device *ccp;
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struct list_head pending;
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struct list_head active;
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enum dma_status status;
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struct dma_async_tx_descriptor tx_desc;
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size_t len;
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};
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struct ccp_dma_chan {
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struct ccp_device *ccp;
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spinlock_t lock;
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struct list_head created;
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struct list_head pending;
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struct list_head active;
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struct list_head complete;
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struct tasklet_struct cleanup_tasklet;
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enum dma_status status;
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struct dma_chan dma_chan;
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};
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struct ccp_cmd_queue {
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struct ccp_device *ccp;
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/* Queue identifier */
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u32 id;
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/* Queue dma pool */
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struct dma_pool *dma_pool;
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/* Queue base address (not neccessarily aligned)*/
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struct ccp5_desc *qbase;
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/* Aligned queue start address (per requirement) */
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struct mutex q_mutex ____cacheline_aligned;
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unsigned int qidx;
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/* Version 5 has different requirements for queue memory */
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unsigned int qsize;
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dma_addr_t qbase_dma;
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dma_addr_t qdma_tail;
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/* Per-queue reserved storage block(s) */
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u32 sb_key;
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u32 sb_ctx;
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/* Bitmap of LSBs that can be accessed by this queue */
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DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
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/* Private LSB that is assigned to this queue, or -1 if none.
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* Bitmap for my private LSB, unused otherwise
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*/
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int lsb;
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DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
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/* Queue processing thread */
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struct task_struct *kthread;
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unsigned int active;
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unsigned int suspended;
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/* Number of free command slots available */
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unsigned int free_slots;
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/* Interrupt masks */
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u32 int_ok;
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u32 int_err;
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/* Register addresses for queue */
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void __iomem *reg_control;
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void __iomem *reg_tail_lo;
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void __iomem *reg_head_lo;
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void __iomem *reg_int_enable;
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void __iomem *reg_interrupt_status;
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void __iomem *reg_status;
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void __iomem *reg_int_status;
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void __iomem *reg_dma_status;
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void __iomem *reg_dma_read_status;
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void __iomem *reg_dma_write_status;
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u32 qcontrol; /* Cached control register */
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/* Status values from job */
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u32 int_status;
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u32 q_status;
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u32 q_int_status;
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u32 cmd_error;
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/* Interrupt wait queue */
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wait_queue_head_t int_queue;
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unsigned int int_rcvd;
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/* Per-queue Statistics */
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unsigned long total_ops;
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unsigned long total_aes_ops;
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unsigned long total_xts_aes_ops;
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unsigned long total_3des_ops;
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unsigned long total_sha_ops;
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unsigned long total_rsa_ops;
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unsigned long total_pt_ops;
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unsigned long total_ecc_ops;
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} ____cacheline_aligned;
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struct ccp_device {
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struct list_head entry;
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struct ccp_vdata *vdata;
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unsigned int ord;
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char name[MAX_CCP_NAME_LEN];
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char rngname[MAX_CCP_NAME_LEN];
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struct device *dev;
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struct sp_device *sp;
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/* Bus specific device information
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*/
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void *dev_specific;
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unsigned int qim;
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unsigned int irq;
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bool use_tasklet;
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struct tasklet_struct irq_tasklet;
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/* I/O area used for device communication. The register mapping
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* starts at an offset into the mapped bar.
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* The CMD_REQx registers and the Delete_Cmd_Queue_Job register
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* need to be protected while a command queue thread is accessing
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* them.
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*/
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struct mutex req_mutex ____cacheline_aligned;
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void __iomem *io_regs;
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/* Master lists that all cmds are queued on. Because there can be
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* more than one CCP command queue that can process a cmd a separate
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* backlog list is needed so that the backlog completion call
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* completes before the cmd is available for execution.
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*/
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spinlock_t cmd_lock ____cacheline_aligned;
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unsigned int cmd_count;
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struct list_head cmd;
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struct list_head backlog;
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/* The command queues. These represent the queues available on the
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* CCP that are available for processing cmds
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*/
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struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
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unsigned int cmd_q_count;
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unsigned int max_q_count;
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/* Support for the CCP True RNG
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*/
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struct hwrng hwrng;
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unsigned int hwrng_retries;
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/* Support for the CCP DMA capabilities
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*/
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struct dma_device dma_dev;
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struct ccp_dma_chan *ccp_dma_chan;
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struct kmem_cache *dma_cmd_cache;
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struct kmem_cache *dma_desc_cache;
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/* A counter used to generate job-ids for cmds submitted to the CCP
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*/
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atomic_t current_id ____cacheline_aligned;
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/* The v3 CCP uses key storage blocks (SB) to maintain context for
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* certain operations. To prevent multiple cmds from using the same
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* SB range a command queue reserves an SB range for the duration of
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* the cmd. Each queue, will however, reserve 2 SB blocks for
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* operations that only require single SB entries (eg. AES context/iv
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* and key) in order to avoid allocation contention. This will reserve
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* at most 10 SB entries, leaving 40 SB entries available for dynamic
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* allocation.
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*
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* The v5 CCP Local Storage Block (LSB) is broken up into 8
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* memrory ranges, each of which can be enabled for access by one
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* or more queues. Device initialization takes this into account,
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* and attempts to assign one region for exclusive use by each
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* available queue; the rest are then aggregated as "public" use.
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* If there are fewer regions than queues, all regions are shared
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* amongst all queues.
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*/
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struct mutex sb_mutex ____cacheline_aligned;
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DECLARE_BITMAP(sb, KSB_COUNT);
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wait_queue_head_t sb_queue;
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unsigned int sb_avail;
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unsigned int sb_count;
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u32 sb_start;
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/* Bitmap of shared LSBs, if any */
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DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
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/* Suspend support */
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unsigned int suspending;
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wait_queue_head_t suspend_queue;
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/* DMA caching attribute support */
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unsigned int axcache;
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/* Device Statistics */
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unsigned long total_interrupts;
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/* DebugFS info */
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struct dentry *debugfs_instance;
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};
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enum ccp_memtype {
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CCP_MEMTYPE_SYSTEM = 0,
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CCP_MEMTYPE_SB,
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CCP_MEMTYPE_LOCAL,
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CCP_MEMTYPE__LAST,
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};
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#define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
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struct ccp_dma_info {
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dma_addr_t address;
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unsigned int offset;
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unsigned int length;
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enum dma_data_direction dir;
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} __packed __aligned(4);
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struct ccp_dm_workarea {
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struct device *dev;
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struct dma_pool *dma_pool;
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u8 *address;
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struct ccp_dma_info dma;
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unsigned int length;
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};
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struct ccp_sg_workarea {
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struct scatterlist *sg;
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int nents;
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unsigned int sg_used;
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struct scatterlist *dma_sg;
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struct scatterlist *dma_sg_head;
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struct device *dma_dev;
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unsigned int dma_count;
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enum dma_data_direction dma_dir;
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u64 bytes_left;
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};
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struct ccp_data {
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struct ccp_sg_workarea sg_wa;
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struct ccp_dm_workarea dm_wa;
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};
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struct ccp_mem {
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enum ccp_memtype type;
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union {
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struct ccp_dma_info dma;
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u32 sb;
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} u;
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};
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struct ccp_aes_op {
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enum ccp_aes_type type;
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enum ccp_aes_mode mode;
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enum ccp_aes_action action;
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unsigned int size;
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};
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struct ccp_xts_aes_op {
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enum ccp_aes_type type;
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enum ccp_aes_action action;
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enum ccp_xts_aes_unit_size unit_size;
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};
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struct ccp_des3_op {
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enum ccp_des3_type type;
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enum ccp_des3_mode mode;
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enum ccp_des3_action action;
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};
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struct ccp_sha_op {
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enum ccp_sha_type type;
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u64 msg_bits;
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};
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struct ccp_rsa_op {
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u32 mod_size;
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u32 input_len;
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};
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struct ccp_passthru_op {
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enum ccp_passthru_bitwise bit_mod;
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enum ccp_passthru_byteswap byte_swap;
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};
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struct ccp_ecc_op {
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enum ccp_ecc_function function;
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|
};
|
|
|
|
struct ccp_op {
|
|
struct ccp_cmd_queue *cmd_q;
|
|
|
|
u32 jobid;
|
|
u32 ioc;
|
|
u32 soc;
|
|
u32 sb_key;
|
|
u32 sb_ctx;
|
|
u32 init;
|
|
u32 eom;
|
|
|
|
struct ccp_mem src;
|
|
struct ccp_mem dst;
|
|
struct ccp_mem exp;
|
|
|
|
union {
|
|
struct ccp_aes_op aes;
|
|
struct ccp_xts_aes_op xts;
|
|
struct ccp_des3_op des3;
|
|
struct ccp_sha_op sha;
|
|
struct ccp_rsa_op rsa;
|
|
struct ccp_passthru_op passthru;
|
|
struct ccp_ecc_op ecc;
|
|
} u;
|
|
};
|
|
|
|
static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
|
|
{
|
|
return lower_32_bits(info->address + info->offset);
|
|
}
|
|
|
|
static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
|
|
{
|
|
return upper_32_bits(info->address + info->offset) & 0x0000ffff;
|
|
}
|
|
|
|
/**
|
|
* descriptor for version 5 CPP commands
|
|
* 8 32-bit words:
|
|
* word 0: function; engine; control bits
|
|
* word 1: length of source data
|
|
* word 2: low 32 bits of source pointer
|
|
* word 3: upper 16 bits of source pointer; source memory type
|
|
* word 4: low 32 bits of destination pointer
|
|
* word 5: upper 16 bits of destination pointer; destination memory type
|
|
* word 6: low 32 bits of key pointer
|
|
* word 7: upper 16 bits of key pointer; key memory type
|
|
*/
|
|
struct dword0 {
|
|
unsigned int soc:1;
|
|
unsigned int ioc:1;
|
|
unsigned int rsvd1:1;
|
|
unsigned int init:1;
|
|
unsigned int eom:1; /* AES/SHA only */
|
|
unsigned int function:15;
|
|
unsigned int engine:4;
|
|
unsigned int prot:1;
|
|
unsigned int rsvd2:7;
|
|
};
|
|
|
|
struct dword3 {
|
|
unsigned int src_hi:16;
|
|
unsigned int src_mem:2;
|
|
unsigned int lsb_cxt_id:8;
|
|
unsigned int rsvd1:5;
|
|
unsigned int fixed:1;
|
|
};
|
|
|
|
union dword4 {
|
|
u32 dst_lo; /* NON-SHA */
|
|
u32 sha_len_lo; /* SHA */
|
|
};
|
|
|
|
union dword5 {
|
|
struct {
|
|
unsigned int dst_hi:16;
|
|
unsigned int dst_mem:2;
|
|
unsigned int rsvd1:13;
|
|
unsigned int fixed:1;
|
|
} fields;
|
|
u32 sha_len_hi;
|
|
};
|
|
|
|
struct dword7 {
|
|
unsigned int key_hi:16;
|
|
unsigned int key_mem:2;
|
|
unsigned int rsvd1:14;
|
|
};
|
|
|
|
struct ccp5_desc {
|
|
struct dword0 dw0;
|
|
u32 length;
|
|
u32 src_lo;
|
|
struct dword3 dw3;
|
|
union dword4 dw4;
|
|
union dword5 dw5;
|
|
u32 key_lo;
|
|
struct dword7 dw7;
|
|
};
|
|
|
|
void ccp_add_device(struct ccp_device *ccp);
|
|
void ccp_del_device(struct ccp_device *ccp);
|
|
|
|
extern void ccp_log_error(struct ccp_device *, unsigned int);
|
|
|
|
struct ccp_device *ccp_alloc_struct(struct sp_device *sp);
|
|
bool ccp_queues_suspended(struct ccp_device *ccp);
|
|
int ccp_cmd_queue_thread(void *data);
|
|
int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
|
|
|
|
int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
|
|
|
|
int ccp_register_rng(struct ccp_device *ccp);
|
|
void ccp_unregister_rng(struct ccp_device *ccp);
|
|
int ccp_dmaengine_register(struct ccp_device *ccp);
|
|
void ccp_dmaengine_unregister(struct ccp_device *ccp);
|
|
|
|
void ccp5_debugfs_setup(struct ccp_device *ccp);
|
|
void ccp5_debugfs_destroy(void);
|
|
|
|
/* Structure for computation functions that are device-specific */
|
|
struct ccp_actions {
|
|
int (*aes)(struct ccp_op *);
|
|
int (*xts_aes)(struct ccp_op *);
|
|
int (*des3)(struct ccp_op *);
|
|
int (*sha)(struct ccp_op *);
|
|
int (*rsa)(struct ccp_op *);
|
|
int (*passthru)(struct ccp_op *);
|
|
int (*ecc)(struct ccp_op *);
|
|
u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
|
|
void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
|
|
unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
|
|
int (*init)(struct ccp_device *);
|
|
void (*destroy)(struct ccp_device *);
|
|
irqreturn_t (*irqhandler)(int, void *);
|
|
};
|
|
|
|
extern const struct ccp_vdata ccpv3_platform;
|
|
extern const struct ccp_vdata ccpv3;
|
|
extern const struct ccp_vdata ccpv5a;
|
|
extern const struct ccp_vdata ccpv5b;
|
|
|
|
#endif
|