293 lines
8.5 KiB
C
293 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA v0 core
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#include <linux/debugfs.h>
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#include <linux/bitfield.h>
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#include "dw-edma-v0-debugfs.h"
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#include "dw-edma-v0-regs.h"
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#include "dw-edma-core.h"
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#define REGS_ADDR(dw, name) \
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({ \
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struct dw_edma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \
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\
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(void __iomem *)&__regs->name; \
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})
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#define REGS_CH_ADDR(dw, name, _dir, _ch) \
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({ \
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struct dw_edma_v0_ch_regs __iomem *__ch_regs; \
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\
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if ((dw)->chip->mf == EDMA_MF_EDMA_LEGACY) \
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__ch_regs = REGS_ADDR(dw, type.legacy.ch); \
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else if (_dir == EDMA_DIR_READ) \
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__ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].rd); \
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else \
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__ch_regs = REGS_ADDR(dw, type.unroll.ch[_ch].wr); \
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\
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(void __iomem *)&__ch_regs->name; \
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})
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#define REGISTER(dw, name) \
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{ dw, #name, REGS_ADDR(dw, name) }
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#define CTX_REGISTER(dw, name, dir, ch) \
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{ dw, #name, REGS_CH_ADDR(dw, name, dir, ch), dir, ch }
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#define WR_REGISTER(dw, name) \
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{ dw, #name, REGS_ADDR(dw, wr_##name) }
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#define RD_REGISTER(dw, name) \
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{ dw, #name, REGS_ADDR(dw, rd_##name) }
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#define WR_REGISTER_LEGACY(dw, name) \
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{ dw, #name, REGS_ADDR(dw, type.legacy.wr_##name) }
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#define RD_REGISTER_LEGACY(name) \
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{ dw, #name, REGS_ADDR(dw, type.legacy.rd_##name) }
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#define WR_REGISTER_UNROLL(dw, name) \
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{ dw, #name, REGS_ADDR(dw, type.unroll.wr_##name) }
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#define RD_REGISTER_UNROLL(dw, name) \
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{ dw, #name, REGS_ADDR(dw, type.unroll.rd_##name) }
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#define WRITE_STR "write"
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#define READ_STR "read"
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#define CHANNEL_STR "channel"
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#define REGISTERS_STR "registers"
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struct dw_edma_debugfs_entry {
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struct dw_edma *dw;
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const char *name;
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void __iomem *reg;
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enum dw_edma_dir dir;
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u16 ch;
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};
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static int dw_edma_debugfs_u32_get(void *data, u64 *val)
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{
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struct dw_edma_debugfs_entry *entry = data;
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struct dw_edma *dw = entry->dw;
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void __iomem *reg = entry->reg;
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if (dw->chip->mf == EDMA_MF_EDMA_LEGACY &&
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reg >= REGS_ADDR(dw, type.legacy.ch)) {
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unsigned long flags;
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u32 viewport_sel;
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viewport_sel = entry->dir == EDMA_DIR_READ ? BIT(31) : 0;
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viewport_sel |= FIELD_PREP(EDMA_V0_VIEWPORT_MASK, entry->ch);
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raw_spin_lock_irqsave(&dw->lock, flags);
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writel(viewport_sel, REGS_ADDR(dw, type.legacy.viewport_sel));
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*val = readl(reg);
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raw_spin_unlock_irqrestore(&dw->lock, flags);
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} else {
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*val = readl(reg);
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}
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_edma_debugfs_u32_get, NULL, "0x%08llx\n");
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static void dw_edma_debugfs_create_x32(struct dw_edma *dw,
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const struct dw_edma_debugfs_entry ini[],
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int nr_entries, struct dentry *dent)
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{
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struct dw_edma_debugfs_entry *entries;
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int i;
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entries = devm_kcalloc(dw->chip->dev, nr_entries, sizeof(*entries),
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GFP_KERNEL);
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if (!entries)
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return;
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for (i = 0; i < nr_entries; i++) {
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entries[i] = ini[i];
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debugfs_create_file_unsafe(entries[i].name, 0444, dent,
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&entries[i], &fops_x32);
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}
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}
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static void dw_edma_debugfs_regs_ch(struct dw_edma *dw, enum dw_edma_dir dir,
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u16 ch, struct dentry *dent)
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{
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struct dw_edma_debugfs_entry debugfs_regs[] = {
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CTX_REGISTER(dw, ch_control1, dir, ch),
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CTX_REGISTER(dw, ch_control2, dir, ch),
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CTX_REGISTER(dw, transfer_size, dir, ch),
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CTX_REGISTER(dw, sar.lsb, dir, ch),
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CTX_REGISTER(dw, sar.msb, dir, ch),
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CTX_REGISTER(dw, dar.lsb, dir, ch),
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CTX_REGISTER(dw, dar.msb, dir, ch),
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CTX_REGISTER(dw, llp.lsb, dir, ch),
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CTX_REGISTER(dw, llp.msb, dir, ch),
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};
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int nr_entries;
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, dent);
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}
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static noinline_for_stack void
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dw_edma_debugfs_regs_wr(struct dw_edma *dw, struct dentry *dent)
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{
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const struct dw_edma_debugfs_entry debugfs_regs[] = {
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/* eDMA global registers */
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WR_REGISTER(dw, engine_en),
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WR_REGISTER(dw, doorbell),
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WR_REGISTER(dw, ch_arb_weight.lsb),
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WR_REGISTER(dw, ch_arb_weight.msb),
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/* eDMA interrupts registers */
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WR_REGISTER(dw, int_status),
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WR_REGISTER(dw, int_mask),
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WR_REGISTER(dw, int_clear),
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WR_REGISTER(dw, err_status),
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WR_REGISTER(dw, done_imwr.lsb),
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WR_REGISTER(dw, done_imwr.msb),
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WR_REGISTER(dw, abort_imwr.lsb),
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WR_REGISTER(dw, abort_imwr.msb),
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WR_REGISTER(dw, ch01_imwr_data),
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WR_REGISTER(dw, ch23_imwr_data),
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WR_REGISTER(dw, ch45_imwr_data),
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WR_REGISTER(dw, ch67_imwr_data),
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WR_REGISTER(dw, linked_list_err_en),
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};
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const struct dw_edma_debugfs_entry debugfs_unroll_regs[] = {
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/* eDMA channel context grouping */
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WR_REGISTER_UNROLL(dw, engine_chgroup),
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WR_REGISTER_UNROLL(dw, engine_hshake_cnt.lsb),
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WR_REGISTER_UNROLL(dw, engine_hshake_cnt.msb),
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WR_REGISTER_UNROLL(dw, ch0_pwr_en),
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WR_REGISTER_UNROLL(dw, ch1_pwr_en),
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WR_REGISTER_UNROLL(dw, ch2_pwr_en),
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WR_REGISTER_UNROLL(dw, ch3_pwr_en),
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WR_REGISTER_UNROLL(dw, ch4_pwr_en),
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WR_REGISTER_UNROLL(dw, ch5_pwr_en),
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WR_REGISTER_UNROLL(dw, ch6_pwr_en),
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WR_REGISTER_UNROLL(dw, ch7_pwr_en),
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};
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struct dentry *regs_dent, *ch_dent;
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int nr_entries, i;
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char name[16];
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regs_dent = debugfs_create_dir(WRITE_STR, dent);
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent);
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if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) {
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nr_entries = ARRAY_SIZE(debugfs_unroll_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_unroll_regs, nr_entries,
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regs_dent);
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}
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for (i = 0; i < dw->wr_ch_cnt; i++) {
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snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
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ch_dent = debugfs_create_dir(name, regs_dent);
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dw_edma_debugfs_regs_ch(dw, EDMA_DIR_WRITE, i, ch_dent);
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}
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}
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static noinline_for_stack void dw_edma_debugfs_regs_rd(struct dw_edma *dw,
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struct dentry *dent)
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{
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const struct dw_edma_debugfs_entry debugfs_regs[] = {
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/* eDMA global registers */
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RD_REGISTER(dw, engine_en),
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RD_REGISTER(dw, doorbell),
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RD_REGISTER(dw, ch_arb_weight.lsb),
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RD_REGISTER(dw, ch_arb_weight.msb),
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/* eDMA interrupts registers */
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RD_REGISTER(dw, int_status),
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RD_REGISTER(dw, int_mask),
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RD_REGISTER(dw, int_clear),
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RD_REGISTER(dw, err_status.lsb),
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RD_REGISTER(dw, err_status.msb),
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RD_REGISTER(dw, linked_list_err_en),
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RD_REGISTER(dw, done_imwr.lsb),
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RD_REGISTER(dw, done_imwr.msb),
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RD_REGISTER(dw, abort_imwr.lsb),
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RD_REGISTER(dw, abort_imwr.msb),
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RD_REGISTER(dw, ch01_imwr_data),
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RD_REGISTER(dw, ch23_imwr_data),
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RD_REGISTER(dw, ch45_imwr_data),
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RD_REGISTER(dw, ch67_imwr_data),
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};
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const struct dw_edma_debugfs_entry debugfs_unroll_regs[] = {
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/* eDMA channel context grouping */
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RD_REGISTER_UNROLL(dw, engine_chgroup),
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RD_REGISTER_UNROLL(dw, engine_hshake_cnt.lsb),
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RD_REGISTER_UNROLL(dw, engine_hshake_cnt.msb),
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RD_REGISTER_UNROLL(dw, ch0_pwr_en),
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RD_REGISTER_UNROLL(dw, ch1_pwr_en),
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RD_REGISTER_UNROLL(dw, ch2_pwr_en),
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RD_REGISTER_UNROLL(dw, ch3_pwr_en),
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RD_REGISTER_UNROLL(dw, ch4_pwr_en),
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RD_REGISTER_UNROLL(dw, ch5_pwr_en),
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RD_REGISTER_UNROLL(dw, ch6_pwr_en),
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RD_REGISTER_UNROLL(dw, ch7_pwr_en),
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};
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struct dentry *regs_dent, *ch_dent;
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int nr_entries, i;
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char name[16];
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regs_dent = debugfs_create_dir(READ_STR, dent);
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent);
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if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) {
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nr_entries = ARRAY_SIZE(debugfs_unroll_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_unroll_regs, nr_entries,
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regs_dent);
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}
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for (i = 0; i < dw->rd_ch_cnt; i++) {
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snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
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ch_dent = debugfs_create_dir(name, regs_dent);
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dw_edma_debugfs_regs_ch(dw, EDMA_DIR_READ, i, ch_dent);
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}
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}
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static void dw_edma_debugfs_regs(struct dw_edma *dw)
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{
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const struct dw_edma_debugfs_entry debugfs_regs[] = {
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REGISTER(dw, ctrl_data_arb_prior),
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REGISTER(dw, ctrl),
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};
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struct dentry *regs_dent;
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int nr_entries;
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regs_dent = debugfs_create_dir(REGISTERS_STR, dw->dma.dbg_dev_root);
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nr_entries = ARRAY_SIZE(debugfs_regs);
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dw_edma_debugfs_create_x32(dw, debugfs_regs, nr_entries, regs_dent);
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dw_edma_debugfs_regs_wr(dw, regs_dent);
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dw_edma_debugfs_regs_rd(dw, regs_dent);
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}
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void dw_edma_v0_debugfs_on(struct dw_edma *dw)
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{
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if (!debugfs_initialized())
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return;
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debugfs_create_u32("mf", 0444, dw->dma.dbg_dev_root, &dw->chip->mf);
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debugfs_create_u16("wr_ch_cnt", 0444, dw->dma.dbg_dev_root, &dw->wr_ch_cnt);
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debugfs_create_u16("rd_ch_cnt", 0444, dw->dma.dbg_dev_root, &dw->rd_ch_cnt);
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dw_edma_debugfs_regs(dw);
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}
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