450 lines
11 KiB
C
450 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
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*/
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#include <linux/kernel.h>
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#include <linux/dmaengine.h>
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#include "ste_dma40.h"
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#include "ste_dma40_ll.h"
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static u8 d40_width_to_bits(enum dma_slave_buswidth width)
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{
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if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
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return STEDMA40_ESIZE_8_BIT;
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else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
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return STEDMA40_ESIZE_16_BIT;
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else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
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return STEDMA40_ESIZE_64_BIT;
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else
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return STEDMA40_ESIZE_32_BIT;
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}
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/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
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void d40_log_cfg(struct stedma40_chan_cfg *cfg,
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u32 *lcsp1, u32 *lcsp3)
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{
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u32 l3 = 0; /* dst */
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u32 l1 = 0; /* src */
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/* src is mem? -> increase address pos */
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if (cfg->dir == DMA_MEM_TO_DEV ||
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cfg->dir == DMA_MEM_TO_MEM)
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l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
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/* dst is mem? -> increase address pos */
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if (cfg->dir == DMA_DEV_TO_MEM ||
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cfg->dir == DMA_MEM_TO_MEM)
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l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
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/* src is hw? -> master port 1 */
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if (cfg->dir == DMA_DEV_TO_MEM ||
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cfg->dir == DMA_DEV_TO_DEV)
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l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
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/* dst is hw? -> master port 1 */
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if (cfg->dir == DMA_MEM_TO_DEV ||
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cfg->dir == DMA_DEV_TO_DEV)
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l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
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l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
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l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
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l3 |= d40_width_to_bits(cfg->dst_info.data_width)
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<< D40_MEM_LCSP3_DCFG_ESIZE_POS;
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l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
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l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
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l1 |= d40_width_to_bits(cfg->src_info.data_width)
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<< D40_MEM_LCSP1_SCFG_ESIZE_POS;
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*lcsp1 = l1;
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*lcsp3 = l3;
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}
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void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
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{
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u32 src = 0;
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u32 dst = 0;
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if ((cfg->dir == DMA_DEV_TO_MEM) ||
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(cfg->dir == DMA_DEV_TO_DEV)) {
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/* Set master port to 1 */
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src |= BIT(D40_SREG_CFG_MST_POS);
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src |= D40_TYPE_TO_EVENT(cfg->dev_type);
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if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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src |= BIT(D40_SREG_CFG_PHY_TM_POS);
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else
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src |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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if ((cfg->dir == DMA_MEM_TO_DEV) ||
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(cfg->dir == DMA_DEV_TO_DEV)) {
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/* Set master port to 1 */
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dst |= BIT(D40_SREG_CFG_MST_POS);
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dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
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if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
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dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
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else
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dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
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}
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/* Interrupt on end of transfer for destination */
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dst |= BIT(D40_SREG_CFG_TIM_POS);
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/* Generate interrupt on error */
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src |= BIT(D40_SREG_CFG_EIM_POS);
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dst |= BIT(D40_SREG_CFG_EIM_POS);
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/* PSIZE */
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if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
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src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
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src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
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dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
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dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
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}
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/* Element size */
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src |= d40_width_to_bits(cfg->src_info.data_width)
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<< D40_SREG_CFG_ESIZE_POS;
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dst |= d40_width_to_bits(cfg->dst_info.data_width)
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<< D40_SREG_CFG_ESIZE_POS;
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/* Set the priority bit to high for the physical channel */
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if (cfg->high_priority) {
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src |= BIT(D40_SREG_CFG_PRI_POS);
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dst |= BIT(D40_SREG_CFG_PRI_POS);
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}
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if (cfg->src_info.big_endian)
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src |= BIT(D40_SREG_CFG_LBE_POS);
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if (cfg->dst_info.big_endian)
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dst |= BIT(D40_SREG_CFG_LBE_POS);
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*src_cfg = src;
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*dst_cfg = dst;
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}
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static int d40_phy_fill_lli(struct d40_phy_lli *lli,
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dma_addr_t data,
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u32 data_size,
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dma_addr_t next_lli,
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u32 reg_cfg,
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struct stedma40_half_channel_info *info,
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unsigned int flags)
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{
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bool addr_inc = flags & LLI_ADDR_INC;
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bool term_int = flags & LLI_TERM_INT;
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unsigned int data_width = info->data_width;
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int psize = info->psize;
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int num_elems;
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if (psize == STEDMA40_PSIZE_PHY_1)
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num_elems = 1;
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else
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num_elems = 2 << psize;
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/* Must be aligned */
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if (!IS_ALIGNED(data, data_width))
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return -EINVAL;
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/* Transfer size can't be smaller than (num_elms * elem_size) */
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if (data_size < num_elems * data_width)
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return -EINVAL;
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/* The number of elements. IE now many chunks */
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lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
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/*
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* Distance to next element sized entry.
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* Usually the size of the element unless you want gaps.
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*/
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if (addr_inc)
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lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
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/* Where the data is */
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lli->reg_ptr = data;
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lli->reg_cfg = reg_cfg;
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/* If this scatter list entry is the last one, no next link */
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if (next_lli == 0)
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lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
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else
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lli->reg_lnk = next_lli;
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/* Set/clear interrupt generation on this link item.*/
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if (term_int)
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lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
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else
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lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
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/*
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* Post link - D40_SREG_LNK_PHY_PRE_POS = 0
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* Relink happens after transfer completion.
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*/
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return 0;
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}
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static int d40_seg_size(int size, int data_width1, int data_width2)
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{
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u32 max_w = max(data_width1, data_width2);
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u32 min_w = min(data_width1, data_width2);
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u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
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if (seg_max > STEDMA40_MAX_SEG_SIZE)
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seg_max -= max_w;
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if (size <= seg_max)
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return size;
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if (size <= 2 * seg_max)
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return ALIGN(size / 2, max_w);
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return seg_max;
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}
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static struct d40_phy_lli *
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d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
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dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
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struct stedma40_half_channel_info *info,
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struct stedma40_half_channel_info *otherinfo,
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unsigned long flags)
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{
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bool lastlink = flags & LLI_LAST_LINK;
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bool addr_inc = flags & LLI_ADDR_INC;
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bool term_int = flags & LLI_TERM_INT;
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bool cyclic = flags & LLI_CYCLIC;
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int err;
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dma_addr_t next = lli_phys;
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int size_rest = size;
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int size_seg = 0;
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/*
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* This piece may be split up based on d40_seg_size(); we only want the
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* term int on the last part.
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*/
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if (term_int)
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flags &= ~LLI_TERM_INT;
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do {
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size_seg = d40_seg_size(size_rest, info->data_width,
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otherinfo->data_width);
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size_rest -= size_seg;
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if (size_rest == 0 && term_int)
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flags |= LLI_TERM_INT;
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if (size_rest == 0 && lastlink)
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next = cyclic ? first_phys : 0;
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else
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next = ALIGN(next + sizeof(struct d40_phy_lli),
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D40_LLI_ALIGN);
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err = d40_phy_fill_lli(lli, addr, size_seg, next,
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reg_cfg, info, flags);
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if (err)
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goto err;
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lli++;
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if (addr_inc)
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addr += size_seg;
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} while (size_rest);
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return lli;
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err:
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return NULL;
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}
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int d40_phy_sg_to_lli(struct scatterlist *sg,
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int sg_len,
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dma_addr_t target,
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struct d40_phy_lli *lli_sg,
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dma_addr_t lli_phys,
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u32 reg_cfg,
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struct stedma40_half_channel_info *info,
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struct stedma40_half_channel_info *otherinfo,
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unsigned long flags)
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{
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int total_size = 0;
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int i;
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struct scatterlist *current_sg = sg;
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struct d40_phy_lli *lli = lli_sg;
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dma_addr_t l_phys = lli_phys;
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if (!target)
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flags |= LLI_ADDR_INC;
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for_each_sg(sg, current_sg, sg_len, i) {
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dma_addr_t sg_addr = sg_dma_address(current_sg);
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unsigned int len = sg_dma_len(current_sg);
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dma_addr_t dst = target ?: sg_addr;
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total_size += sg_dma_len(current_sg);
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if (i == sg_len - 1)
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flags |= LLI_TERM_INT | LLI_LAST_LINK;
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l_phys = ALIGN(lli_phys + (lli - lli_sg) *
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sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
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lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
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reg_cfg, info, otherinfo, flags);
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if (lli == NULL)
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return -EINVAL;
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}
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return total_size;
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}
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/* DMA logical lli operations */
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static void d40_log_lli_link(struct d40_log_lli *lli_dst,
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struct d40_log_lli *lli_src,
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int next, unsigned int flags)
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{
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bool interrupt = flags & LLI_TERM_INT;
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u32 slos = 0;
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u32 dlos = 0;
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if (next != -EINVAL) {
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slos = next * 2;
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dlos = next * 2 + 1;
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}
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if (interrupt) {
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lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
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lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
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}
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lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
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(slos << D40_MEM_LCSP1_SLOS_POS);
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lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
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(dlos << D40_MEM_LCSP1_SLOS_POS);
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}
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void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
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struct d40_log_lli *lli_dst,
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struct d40_log_lli *lli_src,
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int next, unsigned int flags)
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{
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d40_log_lli_link(lli_dst, lli_src, next, flags);
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writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
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writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
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writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
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writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
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}
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void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
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struct d40_log_lli *lli_dst,
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struct d40_log_lli *lli_src,
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int next, unsigned int flags)
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{
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d40_log_lli_link(lli_dst, lli_src, next, flags);
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writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
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writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
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writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
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writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
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}
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static void d40_log_fill_lli(struct d40_log_lli *lli,
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dma_addr_t data, u32 data_size,
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u32 reg_cfg,
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u32 data_width,
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unsigned int flags)
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{
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bool addr_inc = flags & LLI_ADDR_INC;
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lli->lcsp13 = reg_cfg;
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/* The number of elements to transfer */
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lli->lcsp02 = ((data_size / data_width) <<
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D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
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BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
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/* 16 LSBs address of the current element */
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lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
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/* 16 MSBs address of the current element */
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lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
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if (addr_inc)
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lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
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}
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static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
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dma_addr_t addr,
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int size,
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u32 lcsp13, /* src or dst*/
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u32 data_width1,
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u32 data_width2,
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unsigned int flags)
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{
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bool addr_inc = flags & LLI_ADDR_INC;
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struct d40_log_lli *lli = lli_sg;
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int size_rest = size;
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int size_seg = 0;
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do {
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size_seg = d40_seg_size(size_rest, data_width1, data_width2);
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size_rest -= size_seg;
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d40_log_fill_lli(lli,
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addr,
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size_seg,
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lcsp13, data_width1,
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flags);
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if (addr_inc)
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addr += size_seg;
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lli++;
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} while (size_rest);
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return lli;
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}
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int d40_log_sg_to_lli(struct scatterlist *sg,
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int sg_len,
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dma_addr_t dev_addr,
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struct d40_log_lli *lli_sg,
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u32 lcsp13, /* src or dst*/
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u32 data_width1, u32 data_width2)
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{
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int total_size = 0;
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struct scatterlist *current_sg = sg;
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int i;
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struct d40_log_lli *lli = lli_sg;
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unsigned long flags = 0;
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if (!dev_addr)
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flags |= LLI_ADDR_INC;
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for_each_sg(sg, current_sg, sg_len, i) {
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dma_addr_t sg_addr = sg_dma_address(current_sg);
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unsigned int len = sg_dma_len(current_sg);
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dma_addr_t addr = dev_addr ?: sg_addr;
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total_size += sg_dma_len(current_sg);
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lli = d40_log_buf_to_lli(lli, addr, len,
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lcsp13,
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data_width1,
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data_width2,
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flags);
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}
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return total_size;
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}
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