78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_MMHUB_H__
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#define __AMDGPU_MMHUB_H__
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enum amdgpu_mmhub_ras_memory_id {
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AMDGPU_MMHUB_WGMI_PAGEMEM = 0,
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AMDGPU_MMHUB_RGMI_PAGEMEM = 1,
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AMDGPU_MMHUB_WDRAM_PAGEMEM = 2,
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AMDGPU_MMHUB_RDRAM_PAGEMEM = 3,
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AMDGPU_MMHUB_WIO_CMDMEM = 4,
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AMDGPU_MMHUB_RIO_CMDMEM = 5,
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AMDGPU_MMHUB_WGMI_CMDMEM = 6,
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AMDGPU_MMHUB_RGMI_CMDMEM = 7,
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AMDGPU_MMHUB_WDRAM_CMDMEM = 8,
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AMDGPU_MMHUB_RDRAM_CMDMEM = 9,
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AMDGPU_MMHUB_MAM_DMEM0 = 10,
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AMDGPU_MMHUB_MAM_DMEM1 = 11,
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AMDGPU_MMHUB_MAM_DMEM2 = 12,
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AMDGPU_MMHUB_MAM_DMEM3 = 13,
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AMDGPU_MMHUB_WRET_TAGMEM = 19,
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AMDGPU_MMHUB_RRET_TAGMEM = 20,
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AMDGPU_MMHUB_WIO_DATAMEM = 21,
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AMDGPU_MMHUB_WGMI_DATAMEM = 22,
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AMDGPU_MMHUB_WDRAM_DATAMEM = 23,
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AMDGPU_MMHUB_MEMORY_BLOCK_LAST,
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};
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struct amdgpu_mmhub_ras {
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struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_mmhub_funcs {
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u64 (*get_fb_location)(struct amdgpu_device *adev);
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u64 (*get_mc_fb_offset)(struct amdgpu_device *adev);
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void (*init)(struct amdgpu_device *adev);
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int (*gart_enable)(struct amdgpu_device *adev);
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void (*set_fault_enable_default)(struct amdgpu_device *adev,
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bool value);
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void (*gart_disable)(struct amdgpu_device *adev);
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int (*set_clockgating)(struct amdgpu_device *adev,
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enum amd_clockgating_state state);
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void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags);
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void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid,
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uint64_t page_table_base);
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void (*update_power_gating)(struct amdgpu_device *adev,
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bool enable);
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};
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struct amdgpu_mmhub {
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struct ras_common_if *ras_if;
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const struct amdgpu_mmhub_funcs *funcs;
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struct amdgpu_mmhub_ras *ras;
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};
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int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev);
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#endif
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