116 lines
4.6 KiB
C
116 lines
4.6 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_NBIO_H__
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#define __AMDGPU_NBIO_H__
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/*
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* amdgpu nbio functions
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*/
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struct nbio_hdp_flush_reg {
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u32 ref_and_mask_cp0;
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u32 ref_and_mask_cp1;
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u32 ref_and_mask_cp2;
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u32 ref_and_mask_cp3;
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u32 ref_and_mask_cp4;
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u32 ref_and_mask_cp5;
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u32 ref_and_mask_cp6;
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u32 ref_and_mask_cp7;
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u32 ref_and_mask_cp8;
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u32 ref_and_mask_cp9;
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u32 ref_and_mask_sdma0;
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u32 ref_and_mask_sdma1;
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u32 ref_and_mask_sdma2;
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u32 ref_and_mask_sdma3;
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u32 ref_and_mask_sdma4;
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u32 ref_and_mask_sdma5;
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u32 ref_and_mask_sdma6;
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u32 ref_and_mask_sdma7;
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};
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struct amdgpu_nbio_ras {
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struct amdgpu_ras_block_object ras_block;
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void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
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void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
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int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
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int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
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};
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struct amdgpu_nbio_funcs {
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const struct nbio_hdp_flush_reg *hdp_flush_reg;
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u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
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u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
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u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
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u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
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u32 (*get_pcie_index_hi_offset)(struct amdgpu_device *adev);
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u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
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u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
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u32 (*get_rev_id)(struct amdgpu_device *adev);
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void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
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u32 (*get_memsize)(struct amdgpu_device *adev);
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void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index, int doorbell_size);
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void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
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int doorbell_index, int instance);
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void (*gc_doorbell_init)(struct amdgpu_device *adev);
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void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
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bool enable);
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void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
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bool enable);
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void (*ih_doorbell_range)(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index);
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void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
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bool enable);
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void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
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bool enable);
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void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
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bool enable);
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void (*get_clockgating_state)(struct amdgpu_device *adev,
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u64 *flags);
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void (*ih_control)(struct amdgpu_device *adev);
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void (*init_registers)(struct amdgpu_device *adev);
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void (*remap_hdp_registers)(struct amdgpu_device *adev);
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void (*enable_aspm)(struct amdgpu_device *adev,
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bool enable);
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void (*program_aspm)(struct amdgpu_device *adev);
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void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
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void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
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void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
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u32 (*get_rom_offset)(struct amdgpu_device *adev);
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int (*get_compute_partition_mode)(struct amdgpu_device *adev);
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u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,
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u32 *supp_modes);
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};
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struct amdgpu_nbio {
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const struct nbio_hdp_flush_reg *hdp_flush_reg;
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struct amdgpu_irq_src ras_controller_irq;
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struct amdgpu_irq_src ras_err_event_athub_irq;
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struct ras_common_if *ras_if;
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const struct amdgpu_nbio_funcs *funcs;
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struct amdgpu_nbio_ras *ras;
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};
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int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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#endif
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