130 lines
4.1 KiB
C
130 lines
4.1 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_RESET_H__
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#define __AMDGPU_RESET_H__
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#include "amdgpu.h"
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enum AMDGPU_RESET_FLAGS {
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AMDGPU_NEED_FULL_RESET = 0,
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AMDGPU_SKIP_HW_RESET = 1,
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AMDGPU_RESET_FOR_DEVICE_REMOVE = 2,
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};
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struct amdgpu_reset_context {
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enum amd_reset_method method;
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struct amdgpu_device *reset_req_dev;
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struct amdgpu_job *job;
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struct amdgpu_hive_info *hive;
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struct list_head *reset_device_list;
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unsigned long flags;
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};
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struct amdgpu_reset_handler {
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enum amd_reset_method reset_method;
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struct list_head handler_list;
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int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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int (*do_reset)(struct amdgpu_device *adev);
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};
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struct amdgpu_reset_control {
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void *handle;
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struct work_struct reset_work;
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struct mutex reset_lock;
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struct list_head reset_handlers;
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atomic_t in_reset;
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enum amd_reset_method active_reset;
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struct amdgpu_reset_handler *(*get_reset_handler)(
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struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *context);
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void (*async_reset)(struct work_struct *work);
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};
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enum amdgpu_reset_domain_type {
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SINGLE_DEVICE,
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XGMI_HIVE
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};
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struct amdgpu_reset_domain {
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struct kref refcount;
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struct workqueue_struct *wq;
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enum amdgpu_reset_domain_type type;
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struct rw_semaphore sem;
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atomic_t in_gpu_reset;
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atomic_t reset_res;
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};
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int amdgpu_reset_init(struct amdgpu_device *adev);
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int amdgpu_reset_fini(struct amdgpu_device *adev);
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int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context);
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int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context);
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int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_handler *handler);
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struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
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char *wq_name);
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void amdgpu_reset_destroy_reset_domain(struct kref *ref);
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static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
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{
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return kref_get_unless_zero(&domain->refcount) != 0;
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}
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static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
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{
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if (domain)
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kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
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}
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static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
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struct work_struct *work)
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{
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return queue_work(domain->wq, work);
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}
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void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
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void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
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#endif
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