452 lines
16 KiB
C
452 lines
16 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef __AMDGPU_RING_H__
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#define __AMDGPU_RING_H__
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#include <drm/amdgpu_drm.h>
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#include <drm/gpu_scheduler.h>
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#include <drm/drm_print.h>
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#include <drm/drm_suballoc.h>
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struct amdgpu_device;
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struct amdgpu_ring;
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struct amdgpu_ib;
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struct amdgpu_cs_parser;
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struct amdgpu_job;
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struct amdgpu_vm;
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/* max number of rings */
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#define AMDGPU_MAX_RINGS 124
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#define AMDGPU_MAX_HWIP_RINGS 64
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#define AMDGPU_MAX_GFX_RINGS 2
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#define AMDGPU_MAX_SW_GFX_RINGS 2
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#define AMDGPU_MAX_COMPUTE_RINGS 8
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#define AMDGPU_MAX_VCE_RINGS 3
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#define AMDGPU_MAX_UVD_ENC_RINGS 2
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enum amdgpu_ring_priority_level {
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AMDGPU_RING_PRIO_0,
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AMDGPU_RING_PRIO_1,
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AMDGPU_RING_PRIO_DEFAULT = 1,
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AMDGPU_RING_PRIO_2,
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AMDGPU_RING_PRIO_MAX
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};
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/* some special values for the owner field */
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#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
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#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
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#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
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#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
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#define AMDGPU_FENCE_FLAG_INT (1 << 1)
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#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
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#define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
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#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
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#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
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enum amdgpu_ring_type {
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AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
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AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
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AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
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AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
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AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
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AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
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AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
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AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
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AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
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AMDGPU_RING_TYPE_KIQ,
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AMDGPU_RING_TYPE_MES
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};
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enum amdgpu_ib_pool_type {
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/* Normal submissions to the top of the pipeline. */
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AMDGPU_IB_POOL_DELAYED,
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/* Immediate submissions to the bottom of the pipeline. */
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AMDGPU_IB_POOL_IMMEDIATE,
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/* Direct submission to the ring buffer during init and reset. */
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AMDGPU_IB_POOL_DIRECT,
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AMDGPU_IB_POOL_MAX
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};
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struct amdgpu_ib {
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struct drm_suballoc *sa_bo;
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uint32_t length_dw;
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uint64_t gpu_addr;
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uint32_t *ptr;
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uint32_t flags;
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};
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struct amdgpu_sched {
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u32 num_scheds;
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struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
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};
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/*
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* Fences.
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*/
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struct amdgpu_fence_driver {
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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/* sync_seq is protected by ring emission lock */
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uint32_t sync_seq;
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atomic_t last_seq;
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bool initialized;
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struct amdgpu_irq_src *irq_src;
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unsigned irq_type;
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struct timer_list fallback_timer;
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unsigned num_fences_mask;
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spinlock_t lock;
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struct dma_fence **fences;
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};
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extern const struct drm_sched_backend_ops amdgpu_sched_ops;
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void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
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void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
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void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq_src,
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unsigned irq_type);
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void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
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void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
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int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
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void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
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int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
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unsigned flags);
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int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
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uint32_t timeout);
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bool amdgpu_fence_process(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
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uint32_t wait_seq,
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signed long timeout);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
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u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
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void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
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ktime_t timestamp);
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/*
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* Rings.
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*/
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/* provided by hw blocks that expose a ring buffer for commands */
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struct amdgpu_ring_funcs {
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enum amdgpu_ring_type type;
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uint32_t align_mask;
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u32 nop;
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bool support_64bit_ptrs;
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bool no_user_fence;
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bool secure_submission_supported;
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unsigned extra_dw;
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/* ring read/write ptr handling */
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u64 (*get_rptr)(struct amdgpu_ring *ring);
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u64 (*get_wptr)(struct amdgpu_ring *ring);
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void (*set_wptr)(struct amdgpu_ring *ring);
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/* validating and patching of IBs */
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int (*parse_cs)(struct amdgpu_cs_parser *p,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib);
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int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib);
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/* constants to calculate how many DW are needed for an emit */
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unsigned emit_frame_size;
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unsigned emit_ib_size;
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/* command emit functions */
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void (*emit_ib)(struct amdgpu_ring *ring,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib,
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uint32_t flags);
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void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
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uint64_t seq, unsigned flags);
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void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
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void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
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uint64_t pd_addr);
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void (*emit_hdp_flush)(struct amdgpu_ring *ring);
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void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
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uint32_t gds_base, uint32_t gds_size,
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uint32_t gws_base, uint32_t gws_size,
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uint32_t oa_base, uint32_t oa_size);
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/* testing functions */
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int (*test_ring)(struct amdgpu_ring *ring);
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int (*test_ib)(struct amdgpu_ring *ring, long timeout);
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/* insert NOP packets */
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void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
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void (*insert_start)(struct amdgpu_ring *ring);
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void (*insert_end)(struct amdgpu_ring *ring);
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/* pad the indirect buffer to the necessary number of dw */
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void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
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void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
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/* note usage for clock and power gating */
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void (*begin_use)(struct amdgpu_ring *ring);
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void (*end_use)(struct amdgpu_ring *ring);
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void (*emit_switch_buffer) (struct amdgpu_ring *ring);
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void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
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void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
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u64 gds_va, bool init_shadow, int vmid);
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void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t reg_val_offs);
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void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
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void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask);
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void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
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bool secure);
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/* Try to soft recover the ring to make the fence signal */
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void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
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int (*preempt_ib)(struct amdgpu_ring *ring);
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void (*emit_mem_sync)(struct amdgpu_ring *ring);
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void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
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void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
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void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
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void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
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};
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struct amdgpu_ring {
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struct amdgpu_device *adev;
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const struct amdgpu_ring_funcs *funcs;
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struct amdgpu_fence_driver fence_drv;
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struct drm_gpu_scheduler sched;
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struct amdgpu_bo *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr_offs;
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u64 rptr_gpu_addr;
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volatile u32 *rptr_cpu_addr;
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u64 wptr;
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u64 wptr_old;
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unsigned ring_size;
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unsigned max_dw;
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int count_dw;
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uint64_t gpu_addr;
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uint64_t ptr_mask;
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uint32_t buf_mask;
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u32 idx;
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u32 xcc_id;
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u32 xcp_id;
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u32 me;
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u32 pipe;
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u32 queue;
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struct amdgpu_bo *mqd_obj;
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uint64_t mqd_gpu_addr;
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void *mqd_ptr;
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unsigned mqd_size;
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uint64_t eop_gpu_addr;
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u32 doorbell_index;
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bool use_doorbell;
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bool use_pollmem;
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unsigned wptr_offs;
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u64 wptr_gpu_addr;
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volatile u32 *wptr_cpu_addr;
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unsigned fence_offs;
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u64 fence_gpu_addr;
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volatile u32 *fence_cpu_addr;
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uint64_t current_ctx;
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char name[16];
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u32 trail_seq;
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unsigned trail_fence_offs;
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u64 trail_fence_gpu_addr;
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volatile u32 *trail_fence_cpu_addr;
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unsigned cond_exe_offs;
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u64 cond_exe_gpu_addr;
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volatile u32 *cond_exe_cpu_addr;
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unsigned vm_hub;
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unsigned vm_inv_eng;
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struct dma_fence *vmid_wait;
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bool has_compute_vm_bug;
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bool no_scheduler;
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int hw_prio;
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unsigned num_hw_submission;
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atomic_t *sched_score;
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/* used for mes */
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bool is_mes_queue;
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uint32_t hw_queue_id;
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struct amdgpu_mes_ctx_data *mes_ctx;
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bool is_sw_ring;
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unsigned int entry_index;
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};
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#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
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#define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
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#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
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#define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
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#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
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#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
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#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
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#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
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#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
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#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
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#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
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#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
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#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
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#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
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#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
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#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
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#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
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#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
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#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
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#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
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#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
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#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
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#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
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#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
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#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
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#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
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#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
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#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
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unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
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void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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void amdgpu_ring_commit(struct amdgpu_ring *ring);
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void amdgpu_ring_undo(struct amdgpu_ring *ring);
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned int max_dw, struct amdgpu_irq_src *irq_src,
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unsigned int irq_type, unsigned int hw_prio,
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atomic_t *sched_score);
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void amdgpu_ring_fini(struct amdgpu_ring *ring);
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void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t val0,
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uint32_t reg1, uint32_t val1);
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bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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struct dma_fence *fence);
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static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
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bool cond_exec)
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{
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*ring->cond_exe_cpu_addr = cond_exec;
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}
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static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
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{
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int i = 0;
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while (i <= ring->buf_mask)
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ring->ring[i++] = ring->funcs->nop;
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}
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static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
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{
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if (ring->count_dw <= 0)
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DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
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ring->ring[ring->wptr++ & ring->buf_mask] = v;
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ring->wptr &= ring->ptr_mask;
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ring->count_dw--;
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}
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static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
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void *src, int count_dw)
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{
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unsigned occupied, chunk1, chunk2;
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void *dst;
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if (unlikely(ring->count_dw < count_dw))
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DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
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occupied = ring->wptr & ring->buf_mask;
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|
dst = (void *)&ring->ring[occupied];
|
|
chunk1 = ring->buf_mask + 1 - occupied;
|
|
chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
|
|
chunk2 = count_dw - chunk1;
|
|
chunk1 <<= 2;
|
|
chunk2 <<= 2;
|
|
|
|
if (chunk1)
|
|
memcpy(dst, src, chunk1);
|
|
|
|
if (chunk2) {
|
|
src += chunk1;
|
|
dst = (void *)ring->ring;
|
|
memcpy(dst, src, chunk2);
|
|
}
|
|
|
|
ring->wptr += count_dw;
|
|
ring->wptr &= ring->ptr_mask;
|
|
ring->count_dw -= count_dw;
|
|
}
|
|
|
|
#define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset) \
|
|
(ring->is_mes_queue && ring->mes_ctx ? \
|
|
(ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
|
|
|
|
#define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset) \
|
|
(ring->is_mes_queue && ring->mes_ctx ? \
|
|
(void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
|
|
NULL)
|
|
|
|
int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
|
|
|
|
void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
|
|
struct amdgpu_ring *ring);
|
|
|
|
int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
|
|
|
|
static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
|
|
{
|
|
return ib->ptr[idx];
|
|
}
|
|
|
|
static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
|
|
uint32_t value)
|
|
{
|
|
ib->ptr[idx] = value;
|
|
}
|
|
|
|
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
|
|
unsigned size,
|
|
enum amdgpu_ib_pool_type pool,
|
|
struct amdgpu_ib *ib);
|
|
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
|
|
struct dma_fence *f);
|
|
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|
struct amdgpu_ib *ibs, struct amdgpu_job *job,
|
|
struct dma_fence **f);
|
|
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
|
|
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
|
|
int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
|
|
|
|
#endif
|