552 lines
20 KiB
C
552 lines
20 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_rlc.h"
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/**
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* amdgpu_gfx_rlc_enter_safe_mode - Set RLC into safe mode
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*
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* @adev: amdgpu_device pointer
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* @xcc_id: xcc accelerated compute core id
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*
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* Set RLC enter into safe mode if RLC is enabled and haven't in safe mode.
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*/
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void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id)
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{
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if (adev->gfx.rlc.in_safe_mode[xcc_id])
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return;
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/* if RLC is not enabled, do nothing */
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if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
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return;
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if (adev->cg_flags &
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(AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_3D_CGCG)) {
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adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id);
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adev->gfx.rlc.in_safe_mode[xcc_id] = true;
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}
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}
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/**
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* amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode
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*
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* @adev: amdgpu_device pointer
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* @xcc_id: xcc accelerated compute core id
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*
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* Set RLC exit safe mode if RLC is enabled and have entered into safe mode.
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*/
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void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id)
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{
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if (!(adev->gfx.rlc.in_safe_mode[xcc_id]))
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return;
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/* if RLC is not enabled, do nothing */
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if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
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return;
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if (adev->cg_flags &
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(AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_3D_CGCG)) {
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adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id);
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adev->gfx.rlc.in_safe_mode[xcc_id] = false;
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}
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}
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/**
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* amdgpu_gfx_rlc_init_sr - Init save restore block
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*
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* @adev: amdgpu_device pointer
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* @dws: the size of save restore block
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*
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* Allocate and setup value to save restore block of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)
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{
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const u32 *src_ptr;
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volatile u32 *dst_ptr;
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u32 i;
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int r;
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/* allocate save restore block */
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r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->gfx.rlc.save_restore_obj,
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&adev->gfx.rlc.save_restore_gpu_addr,
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(void **)&adev->gfx.rlc.sr_ptr);
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if (r) {
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dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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/* write the sr buffer */
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src_ptr = adev->gfx.rlc.reg_list;
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dst_ptr = adev->gfx.rlc.sr_ptr;
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for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
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dst_ptr[i] = cpu_to_le32(src_ptr[i]);
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amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_init_csb - Init clear state block
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate and setup value to clear state block of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
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{
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u32 dws;
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int r;
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/* allocate clear state block */
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adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
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r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_init_cpt - Init cp table
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate and setup value to cp table of rlc.
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* Returns 0 on succeess or negative error code if allocate failed.
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*/
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int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
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AMDGPU_GEM_DOMAIN_GTT,
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&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create cp table bo\n", r);
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amdgpu_gfx_rlc_fini(adev);
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return r;
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}
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/* set up the cp table */
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amdgpu_gfx_rlc_setup_cp_table(adev);
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amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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return 0;
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}
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/**
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* amdgpu_gfx_rlc_setup_cp_table - setup cp the buffer of cp table
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*
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* @adev: amdgpu_device pointer
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*
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* Write cp firmware data into cp table.
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*/
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void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev)
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{
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const __le32 *fw_data;
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volatile u32 *dst_ptr;
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int me, i, max_me;
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u32 bo_offset = 0;
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u32 table_offset, table_size;
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max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev);
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/* write the cp table buffer */
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dst_ptr = adev->gfx.rlc.cp_table_ptr;
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for (me = 0; me < max_me; me++) {
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if (me == 0) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.ce_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 1) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.pfp_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 2) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.me_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 3) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 4) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec2_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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}
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for (i = 0; i < table_size; i ++) {
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dst_ptr[bo_offset + i] =
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cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
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}
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bo_offset += table_size;
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}
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}
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/**
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* amdgpu_gfx_rlc_fini - Free BO which used for RLC
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*
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* @adev: amdgpu_device pointer
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*
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* Free three BO which is used for rlc_save_restore_block, rlc_clear_state_block
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* and rlc_jump_table_block.
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*/
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void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev)
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{
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/* save restore block */
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if (adev->gfx.rlc.save_restore_obj) {
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amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj,
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&adev->gfx.rlc.save_restore_gpu_addr,
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(void **)&adev->gfx.rlc.sr_ptr);
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}
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/* clear state block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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/* jump table block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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}
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static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev)
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{
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const struct common_firmware_header *common_hdr;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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unsigned int *tmp;
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unsigned int i;
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rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
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adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
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adev->gfx.rlc.save_and_restore_offset =
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le32_to_cpu(rlc_hdr->save_and_restore_offset);
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adev->gfx.rlc.clear_state_descriptor_offset =
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
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adev->gfx.rlc.avail_scratch_ram_locations =
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
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adev->gfx.rlc.reg_restore_list_size =
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le32_to_cpu(rlc_hdr->reg_restore_list_size);
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adev->gfx.rlc.reg_list_format_start =
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le32_to_cpu(rlc_hdr->reg_list_format_start);
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adev->gfx.rlc.reg_list_format_separate_start =
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le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
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adev->gfx.rlc.starting_offsets_start =
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le32_to_cpu(rlc_hdr->starting_offsets_start);
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adev->gfx.rlc.reg_list_format_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
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adev->gfx.rlc.reg_list_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_size_bytes);
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adev->gfx.rlc.register_list_format =
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kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
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adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
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if (!adev->gfx.rlc.register_list_format) {
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dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n");
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return -ENOMEM;
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}
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
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for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
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adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
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adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
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for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
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adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
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info->fw = adev->gfx.rlc_fw;
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if (info->fw) {
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common_hdr = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(common_hdr->ucode_size_bytes), PAGE_SIZE);
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}
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}
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return 0;
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}
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static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_1 *rlc_hdr;
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struct amdgpu_firmware_info *info;
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rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
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adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
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adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
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adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
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adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
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adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
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adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
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adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
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adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
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adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
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adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
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adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
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adev->gfx.rlc.reg_list_format_direct_reg_list_length =
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le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
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}
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if (adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
|
|
info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev)
|
|
{
|
|
const struct rlc_firmware_header_v2_2 *rlc_hdr;
|
|
struct amdgpu_firmware_info *info;
|
|
|
|
rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
|
|
adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
|
|
adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
|
|
adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
|
|
adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
|
|
|
|
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
|
|
if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
|
|
info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
|
|
info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev)
|
|
{
|
|
const struct rlc_firmware_header_v2_3 *rlc_hdr;
|
|
struct amdgpu_firmware_info *info;
|
|
|
|
rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
|
|
adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version);
|
|
adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version);
|
|
adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes);
|
|
adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);
|
|
|
|
adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version);
|
|
adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version);
|
|
adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes);
|
|
adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);
|
|
|
|
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
|
|
if (adev->gfx.rlc.rlcp_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P];
|
|
info->ucode_id = AMDGPU_UCODE_ID_RLC_P;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.rlcv_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V];
|
|
info->ucode_id = AMDGPU_UCODE_ID_RLC_V;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev)
|
|
{
|
|
const struct rlc_firmware_header_v2_4 *rlc_hdr;
|
|
struct amdgpu_firmware_info *info;
|
|
|
|
rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
|
|
adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
|
|
adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
|
|
adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
|
|
adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
|
|
adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
|
|
adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
|
|
adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
|
|
adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
|
|
adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
|
|
adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
|
|
|
|
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
|
|
if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
|
|
info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
|
|
info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
|
|
info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
|
|
info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
|
|
if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
|
|
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
|
|
info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
|
|
info->fw = adev->gfx.rlc_fw;
|
|
adev->firmware.fw_size +=
|
|
ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
|
|
}
|
|
}
|
|
}
|
|
|
|
int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
|
|
uint16_t version_major,
|
|
uint16_t version_minor)
|
|
{
|
|
int err;
|
|
|
|
if (version_major < 2) {
|
|
/* only support rlc_hdr v2.x and onwards */
|
|
dev_err(adev->dev, "unsupported rlc fw hdr\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* is_rlc_v2_1 is still used in APU code path */
|
|
if (version_major == 2 && version_minor == 1)
|
|
adev->gfx.rlc.is_rlc_v2_1 = true;
|
|
|
|
if (version_minor >= 0) {
|
|
err = amdgpu_gfx_rlc_init_microcode_v2_0(adev);
|
|
if (err) {
|
|
dev_err(adev->dev, "fail to init rlc v2_0 microcode\n");
|
|
return err;
|
|
}
|
|
}
|
|
if (version_minor >= 1)
|
|
amdgpu_gfx_rlc_init_microcode_v2_1(adev);
|
|
if (version_minor >= 2)
|
|
amdgpu_gfx_rlc_init_microcode_v2_2(adev);
|
|
if (version_minor == 3)
|
|
amdgpu_gfx_rlc_init_microcode_v2_3(adev);
|
|
if (version_minor == 4)
|
|
amdgpu_gfx_rlc_init_microcode_v2_4(adev);
|
|
|
|
return 0;
|
|
}
|