580 lines
20 KiB
C
580 lines
20 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v2_3.h"
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#include "nbio/nbio_2_3_default.h"
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#include "nbio/nbio_2_3_offset.h"
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#include "nbio/nbio_2_3_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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#include <linux/pci.h>
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#define smnPCIE_CONFIG_CNTL 0x11180044
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_LC_CNTL 0x11140280
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#define smnPCIE_LC_CNTL3 0x111402d4
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#define smnPCIE_LC_CNTL6 0x111402ec
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#define smnPCIE_LC_CNTL7 0x111402f0
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#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
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#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
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#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
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#define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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#define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6
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#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2
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#define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7
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#define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2
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#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8
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#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
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#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
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static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp;
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/*
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* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
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* therefore we force rev_id to 0 (which is the default value)
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*/
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if (amdgpu_sriov_vf(adev)) {
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return 0;
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}
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tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
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BIF_FB_EN__FB_READ_EN_MASK |
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BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
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}
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static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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}
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static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index,
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int doorbell_size)
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{
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u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
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instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) :
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instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) :
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE);
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u32 doorbell_range = RREG32(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_SDMA0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_SDMA0_DOORBELL_RANGE, SIZE,
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doorbell_size);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_SDMA0_DOORBELL_RANGE, SIZE,
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0);
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WREG32(reg, doorbell_range);
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}
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static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
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int doorbell_index, int instance)
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{
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u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
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u32 doorbell_range = RREG32(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
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WREG32(reg, doorbell_range);
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}
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static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN,
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enable ? 1 : 0);
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}
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static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
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tmp);
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}
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static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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BIF_IH_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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BIF_IH_DOORBELL_RANGE, SIZE,
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2);
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} else
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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BIF_IH_DOORBELL_RANGE, SIZE,
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0);
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WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
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}
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static void nbio_v2_3_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
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/*
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
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IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
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IH_REQ_NONSNOOP_EN, 0);
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
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}
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static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
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return;
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def = data = RREG32_PCIE(smnCPM_CONTROL);
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if (enable) {
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data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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} else {
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data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnCPM_CONTROL, data);
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}
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static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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return;
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def = data = RREG32_PCIE(smnPCIE_CNTL2);
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if (enable) {
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnPCIE_CNTL2, data);
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}
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static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_BIF_MGCG */
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data = RREG32_PCIE(smnCPM_CONTROL);
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if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_MGCG;
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/* AMD_CG_SUPPORT_BIF_LS */
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data = RREG32_PCIE(smnPCIE_CNTL2);
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if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_LS;
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}
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static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
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}
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static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
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}
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static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
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}
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static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
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}
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const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = {
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.ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
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.ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
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.ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
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.ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
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.ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
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.ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
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.ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
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.ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
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.ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
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.ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
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.ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
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.ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
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};
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static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
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if (def != data)
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WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
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if (amdgpu_sriov_vf(adev))
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adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
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}
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#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
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#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x0000000A // 1=1us, 9=1ms, 10=4ms
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#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 400ms
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static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
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if (enable) {
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/* Disable ASPM L0s/L1 first */
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data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
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data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
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if (pci_is_thunderbolt_attached(adev->pdev))
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data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
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else
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data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
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data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
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} else {
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/* Disbale ASPM L1 */
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data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
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/* Disable ASPM TxL0s */
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data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
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/* Disable ACPI L1 */
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data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
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}
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if (def != data)
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WREG32_PCIE(smnPCIE_LC_CNTL, data);
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}
|
|
|
|
#ifdef CONFIG_PCIEASPM
|
|
static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
|
|
{
|
|
uint32_t def, data;
|
|
|
|
WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);
|
|
data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data);
|
|
|
|
def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
|
|
data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
|
|
|
|
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
|
|
data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
|
}
|
|
#endif
|
|
|
|
static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
|
{
|
|
#ifdef CONFIG_PCIEASPM
|
|
uint32_t def, data;
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
|
|
data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
|
|
data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
|
|
data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL, data);
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
|
|
data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL7, data);
|
|
|
|
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
|
|
data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
|
|
data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
|
|
data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
|
|
data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
|
|
data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
|
|
|
|
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
|
|
data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
|
|
|
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
|
|
|
|
def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
|
|
data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
|
|
PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
|
|
data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
|
|
data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
|
|
PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL6, data);
|
|
|
|
/* Don't bother about LTR if LTR is not enabled
|
|
* in the path */
|
|
if (adev->pdev->ltr_path)
|
|
nbio_v2_3_program_ltr(adev);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
|
|
data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
|
data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
|
|
|
|
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
|
|
data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
|
|
if (def != data)
|
|
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
|
|
data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
|
|
if (pci_is_thunderbolt_attached(adev->pdev))
|
|
data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
|
|
else
|
|
data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
|
|
data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL, data);
|
|
|
|
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
|
|
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
|
if (def != data)
|
|
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
|
#endif
|
|
}
|
|
|
|
static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
|
|
{
|
|
uint32_t reg_data = 0;
|
|
uint32_t link_width = 0;
|
|
|
|
if (!((adev->asic_type >= CHIP_NAVI10) &&
|
|
(adev->asic_type <= CHIP_NAVI12)))
|
|
return;
|
|
|
|
reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
|
|
link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
|
|
>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
|
|
|
|
/*
|
|
* Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data)
|
|
* if link_width is 0x3 (x4)
|
|
*/
|
|
if (0x3 == link_width) {
|
|
reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6);
|
|
reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK;
|
|
reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT);
|
|
WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data);
|
|
}
|
|
}
|
|
|
|
static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev)
|
|
{
|
|
uint32_t reg_data = 0;
|
|
|
|
if (adev->asic_type != CHIP_NAVI10)
|
|
return;
|
|
|
|
reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
|
|
reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK;
|
|
WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
|
|
}
|
|
|
|
static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
|
|
{
|
|
uint32_t reg, reg_data;
|
|
|
|
if (adev->ip_versions[NBIO_HWIP][0] != IP_VERSION(3, 3, 0))
|
|
return;
|
|
|
|
reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
|
|
|
|
/* Clear Interrupt Status
|
|
*/
|
|
if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) {
|
|
reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
|
|
if (reg & BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) {
|
|
reg_data = 1 << BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT;
|
|
WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, reg_data);
|
|
}
|
|
}
|
|
}
|
|
|
|
const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
|
|
.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
|
|
.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
|
|
.get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
|
|
.get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset,
|
|
.get_rev_id = nbio_v2_3_get_rev_id,
|
|
.mc_access_enable = nbio_v2_3_mc_access_enable,
|
|
.get_memsize = nbio_v2_3_get_memsize,
|
|
.sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range,
|
|
.vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range,
|
|
.enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture,
|
|
.enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture,
|
|
.ih_doorbell_range = nbio_v2_3_ih_doorbell_range,
|
|
.update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating,
|
|
.update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep,
|
|
.get_clockgating_state = nbio_v2_3_get_clockgating_state,
|
|
.ih_control = nbio_v2_3_ih_control,
|
|
.init_registers = nbio_v2_3_init_registers,
|
|
.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
|
|
.enable_aspm = nbio_v2_3_enable_aspm,
|
|
.program_aspm = nbio_v2_3_program_aspm,
|
|
.apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
|
|
.apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa,
|
|
.clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,
|
|
};
|