142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMD_PCIE_HELPERS_H__
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#define __AMD_PCIE_HELPERS_H__
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#include "amd_pcie.h"
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static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
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{
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if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
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return true;
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return false;
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}
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static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
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{
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if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
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return true;
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return false;
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}
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/* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
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static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
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uint16_t ns_pcie_gen)
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{
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uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
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CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
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uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &
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CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
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switch (asic_pcie_link_speed_cap) {
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case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
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return PP_PCIEGen1;
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case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
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return PP_PCIEGen2;
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case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
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return PP_PCIEGen3;
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default:
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if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
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(ns_pcie_gen == PP_PCIEGen3)) {
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return PP_PCIEGen3;
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} else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
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((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
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return PP_PCIEGen2;
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}
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}
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return PP_PCIEGen1;
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}
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static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
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uint16_t ns_pcie_lanes)
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{
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int i, j;
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uint16_t new_pcie_lanes = ns_pcie_lanes;
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uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
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switch (pcie_lane_width_cap) {
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case 0:
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pr_err("No valid PCIE lane width reported\n");
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
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new_pcie_lanes = 1;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
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new_pcie_lanes = 2;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
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new_pcie_lanes = 4;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
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new_pcie_lanes = 8;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
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new_pcie_lanes = 12;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
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new_pcie_lanes = 16;
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break;
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case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
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new_pcie_lanes = 32;
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break;
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default:
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for (i = 0; i < 7; i++) {
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if (ns_pcie_lanes == pcie_lanes[i]) {
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if (pcie_lane_width_cap & (0x10000 << i)) {
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break;
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} else {
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for (j = i - 1; j >= 0; j--) {
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if (pcie_lane_width_cap & (0x10000 << j)) {
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new_pcie_lanes = pcie_lanes[j];
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break;
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}
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}
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if (j < 0) {
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for (j = i + 1; j < 7; j++) {
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if (pcie_lane_width_cap & (0x10000 << j)) {
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new_pcie_lanes = pcie_lanes[j];
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break;
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}
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}
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if (j > 7)
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pr_err("Cannot find a valid PCIE lane width!\n");
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}
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}
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break;
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}
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}
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break;
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}
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return new_pcie_lanes;
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}
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#endif
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