627 lines
16 KiB
C
627 lines
16 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __MES_API_DEF_H__
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#define __MES_API_DEF_H__
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#pragma pack(push, 4)
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#define MES_API_VERSION 1
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/* Driver submits one API(cmd) as a single Frame and this command size is same
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* for all API to ease the debugging and parsing of ring buffer.
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*/
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enum { API_FRAME_SIZE_IN_DWORDS = 64 };
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/* To avoid command in scheduler context to be overwritten whenenver mutilple
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* interrupts come in, this creates another queue.
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*/
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enum { API_NUMBER_OF_COMMAND_MAX = 32 };
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enum MES_API_TYPE {
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MES_API_TYPE_SCHEDULER = 1,
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MES_API_TYPE_MAX
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};
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enum MES_SCH_API_OPCODE {
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MES_SCH_API_SET_HW_RSRC = 0,
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MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
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MES_SCH_API_ADD_QUEUE = 2,
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MES_SCH_API_REMOVE_QUEUE = 3,
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MES_SCH_API_PERFORM_YIELD = 4,
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MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
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MES_SCH_API_SUSPEND = 6,
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MES_SCH_API_RESUME = 7,
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MES_SCH_API_RESET = 8,
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MES_SCH_API_SET_LOG_BUFFER = 9,
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MES_SCH_API_CHANGE_GANG_PRORITY = 10,
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MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
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MES_SCH_API_PROGRAM_GDS = 12,
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MES_SCH_API_SET_DEBUG_VMID = 13,
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MES_SCH_API_MISC = 14,
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MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
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MES_SCH_API_AMD_LOG = 16,
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MES_SCH_API_MAX = 0xFF
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};
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union MES_API_HEADER {
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struct {
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uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
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uint32_t opcode : 8;
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uint32_t dwsize : 8; /* including header */
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uint32_t reserved : 12;
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};
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uint32_t u32All;
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};
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enum MES_AMD_PRIORITY_LEVEL {
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AMD_PRIORITY_LEVEL_LOW = 0,
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AMD_PRIORITY_LEVEL_NORMAL = 1,
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AMD_PRIORITY_LEVEL_MEDIUM = 2,
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AMD_PRIORITY_LEVEL_HIGH = 3,
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AMD_PRIORITY_LEVEL_REALTIME = 4,
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AMD_PRIORITY_NUM_LEVELS
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};
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enum MES_QUEUE_TYPE {
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MES_QUEUE_TYPE_GFX,
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MES_QUEUE_TYPE_COMPUTE,
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MES_QUEUE_TYPE_SDMA,
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MES_QUEUE_TYPE_MAX,
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};
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struct MES_API_STATUS {
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uint64_t api_completion_fence_addr;
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uint64_t api_completion_fence_value;
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};
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enum { MAX_COMPUTE_PIPES = 8 };
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enum { MAX_GFX_PIPES = 2 };
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enum { MAX_SDMA_PIPES = 2 };
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enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
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enum { MAX_GFX_HQD_PER_PIPE = 8 };
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enum { MAX_SDMA_HQD_PER_PIPE = 10 };
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enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
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enum { MAX_QUEUES_IN_A_GANG = 8 };
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enum VM_HUB_TYPE {
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VM_HUB_TYPE_GC = 0,
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VM_HUB_TYPE_MM = 1,
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VM_HUB_TYPE_MAX,
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};
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enum { VMID_INVALID = 0xffff };
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enum { MAX_VMID_GCHUB = 16 };
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enum { MAX_VMID_MMHUB = 16 };
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enum SET_DEBUG_VMID_OPERATIONS {
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DEBUG_VMID_OP_PROGRAM = 0,
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DEBUG_VMID_OP_ALLOCATE = 1,
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DEBUG_VMID_OP_RELEASE = 2
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};
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enum MES_LOG_OPERATION {
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MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
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MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
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MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
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MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
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MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
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MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
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};
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enum MES_LOG_CONTEXT_STATE {
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MES_LOG_CONTEXT_STATE_IDLE = 0,
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MES_LOG_CONTEXT_STATE_RUNNING = 1,
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MES_LOG_CONTEXT_STATE_READY = 2,
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MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
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MES_LOG_CONTEXT_STATE_INVALID = 0xF,
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};
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struct MES_LOG_CONTEXT_STATE_CHANGE {
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void *h_context;
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enum MES_LOG_CONTEXT_STATE new_context_state;
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};
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struct MES_LOG_QUEUE_NEW_WORK {
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uint64_t h_queue;
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uint64_t reserved;
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};
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struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
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uint64_t h_queue;
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uint64_t h_sync_object;
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};
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struct MES_LOG_QUEUE_NO_MORE_WORK {
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uint64_t h_queue;
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uint64_t reserved;
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};
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struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
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uint64_t h_queue;
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uint64_t h_sync_object;
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};
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struct MES_LOG_ENTRY_HEADER {
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uint32_t first_free_entry_index;
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uint32_t wraparound_count;
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uint64_t number_of_entries;
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uint64_t reserved[2];
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};
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struct MES_LOG_ENTRY_DATA {
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uint64_t gpu_time_stamp;
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uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
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uint32_t reserved_operation_type_bits;
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union {
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struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
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struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
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struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
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struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
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struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
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uint64_t all[2];
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};
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};
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struct MES_LOG_BUFFER {
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struct MES_LOG_ENTRY_HEADER header;
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struct MES_LOG_ENTRY_DATA entries[1];
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};
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enum MES_SWIP_TO_HWIP_DEF {
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MES_MAX_HWIP_SEGMENT = 8,
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};
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union MESAPI_SET_HW_RESOURCES {
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struct {
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union MES_API_HEADER header;
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uint32_t vmid_mask_mmhub;
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uint32_t vmid_mask_gfxhub;
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uint32_t gds_size;
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uint32_t paging_vmid;
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uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
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uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
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uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
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uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
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uint64_t g_sch_ctx_gpu_mc_ptr;
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uint64_t query_status_fence_gpu_mc_ptr;
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uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
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uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
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uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
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struct MES_API_STATUS api_status;
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union {
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struct {
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uint32_t disable_reset : 1;
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uint32_t use_different_vmid_compute : 1;
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uint32_t disable_mes_log : 1;
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uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
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uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
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uint32_t second_gfx_pipe_enabled : 1;
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uint32_t enable_level_process_quantum_check : 1;
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uint32_t legacy_sch_mode : 1;
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uint32_t disable_add_queue_wptr_mc_addr : 1;
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uint32_t enable_mes_event_int_logging : 1;
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uint32_t enable_reg_active_poll : 1;
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uint32_t reserved : 21;
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};
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uint32_t uint32_t_all;
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};
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uint32_t oversubscription_timer;
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uint64_t doorbell_info;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__ADD_QUEUE {
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struct {
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union MES_API_HEADER header;
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uint32_t process_id;
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uint64_t page_table_base_addr;
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uint64_t process_va_start;
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uint64_t process_va_end;
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uint64_t process_quantum;
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uint64_t process_context_addr;
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uint64_t gang_quantum;
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uint64_t gang_context_addr;
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uint32_t inprocess_gang_priority;
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enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
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uint32_t doorbell_offset;
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uint64_t mqd_addr;
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uint64_t wptr_addr;
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uint64_t h_context;
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uint64_t h_queue;
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enum MES_QUEUE_TYPE queue_type;
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uint32_t gds_base;
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uint32_t gds_size;
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uint32_t gws_base;
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uint32_t gws_size;
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uint32_t oa_mask;
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uint64_t trap_handler_addr;
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uint32_t vm_context_cntl;
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struct {
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uint32_t paging : 1;
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uint32_t debug_vmid : 4;
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uint32_t program_gds : 1;
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uint32_t is_gang_suspended : 1;
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uint32_t is_tmz_queue : 1;
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uint32_t map_kiq_utility_queue : 1;
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uint32_t is_kfd_process : 1;
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uint32_t trap_en : 1;
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uint32_t is_aql_queue : 1;
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uint32_t skip_process_ctx_clear : 1;
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uint32_t reserved : 19;
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};
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struct MES_API_STATUS api_status;
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uint64_t tma_addr;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__REMOVE_QUEUE {
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struct {
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union MES_API_HEADER header;
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uint32_t doorbell_offset;
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uint64_t gang_context_addr;
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struct {
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uint32_t unmap_legacy_gfx_queue : 1;
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uint32_t unmap_kiq_utility_queue : 1;
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uint32_t preempt_legacy_gfx_queue : 1;
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uint32_t unmap_legacy_queue : 1;
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uint32_t reserved : 28;
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};
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struct MES_API_STATUS api_status;
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uint32_t pipe_id;
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uint32_t queue_id;
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uint64_t tf_addr;
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uint32_t tf_data;
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enum MES_QUEUE_TYPE queue_type;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SET_SCHEDULING_CONFIG {
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struct {
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union MES_API_HEADER header;
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/* Grace period when preempting another priority band for this
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* priority band. The value for idle priority band is ignored,
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* as it never preempts other bands.
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*/
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uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
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/* Default quantum for scheduling across processes within
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* a priority band.
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*/
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uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
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/* Default grace period for processes that preempt each other
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* within a priority band.
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*/
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uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
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/* For normal level this field specifies the target GPU
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* percentage in situations when it's starved by the high level.
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* Valid values are between 0 and 50, with the default being 10.
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*/
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uint32_t normal_yield_percent;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__PERFORM_YIELD {
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struct {
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union MES_API_HEADER header;
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uint32_t dummy;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
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struct {
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union MES_API_HEADER header;
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uint32_t inprocess_gang_priority;
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enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
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uint64_t gang_quantum;
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uint64_t gang_context_addr;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SUSPEND {
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struct {
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union MES_API_HEADER header;
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/* false - suspend all gangs; true - specific gang */
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struct {
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uint32_t suspend_all_gangs : 1;
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uint32_t reserved : 31;
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};
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/* gang_context_addr is valid only if suspend_all = false */
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uint64_t gang_context_addr;
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uint64_t suspend_fence_addr;
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uint32_t suspend_fence_value;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__RESUME {
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struct {
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union MES_API_HEADER header;
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/* false - resume all gangs; true - specified gang */
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struct {
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uint32_t resume_all_gangs : 1;
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uint32_t reserved : 31;
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};
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/* valid only if resume_all_gangs = false */
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uint64_t gang_context_addr;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__RESET {
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struct {
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union MES_API_HEADER header;
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struct {
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/* Only reset the queue given by doorbell_offset (not entire gang) */
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uint32_t reset_queue_only : 1;
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/* Hang detection first then reset any queues that are hung */
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uint32_t hang_detect_then_reset : 1;
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/* Only do hang detection (no reset) */
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uint32_t hang_detect_only : 1;
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/* Rest HP and LP kernel queues not managed by MES */
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uint32_t reset_legacy_gfx : 1;
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uint32_t reserved : 28;
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};
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uint64_t gang_context_addr;
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/* valid only if reset_queue_only = true */
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uint32_t doorbell_offset;
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/* valid only if hang_detect_then_reset = true */
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uint64_t doorbell_offset_addr;
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enum MES_QUEUE_TYPE queue_type;
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/* valid only if reset_legacy_gfx = true */
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uint32_t pipe_id_lp;
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uint32_t queue_id_lp;
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uint32_t vmid_id_lp;
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uint64_t mqd_mc_addr_lp;
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uint32_t doorbell_offset_lp;
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uint64_t wptr_addr_lp;
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uint32_t pipe_id_hp;
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uint32_t queue_id_hp;
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uint32_t vmid_id_hp;
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uint64_t mqd_mc_addr_hp;
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uint32_t doorbell_offset_hp;
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uint64_t wptr_addr_hp;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__SET_LOGGING_BUFFER {
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struct {
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union MES_API_HEADER header;
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/* There are separate log buffers for each queue type */
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enum MES_QUEUE_TYPE log_type;
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/* Log buffer GPU Address */
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uint64_t logging_buffer_addr;
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/* number of entries in the log buffer */
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uint32_t number_of_entries;
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/* Entry index at which CPU interrupt needs to be signalled */
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uint32_t interrupt_entry;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__QUERY_MES_STATUS {
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struct {
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union MES_API_HEADER header;
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bool mes_healthy; /* 0 - not healthy, 1 - healthy */
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__PROGRAM_GDS {
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struct {
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union MES_API_HEADER header;
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uint64_t process_context_addr;
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uint32_t gds_base;
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uint32_t gds_size;
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uint32_t gws_base;
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uint32_t gws_size;
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uint32_t oa_mask;
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struct MES_API_STATUS api_status;
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
|
|
};
|
|
|
|
union MESAPI__SET_DEBUG_VMID {
|
|
struct {
|
|
union MES_API_HEADER header;
|
|
struct MES_API_STATUS api_status;
|
|
union {
|
|
struct {
|
|
uint32_t use_gds : 1;
|
|
uint32_t operation : 2;
|
|
uint32_t reserved : 29;
|
|
} flags;
|
|
uint32_t u32All;
|
|
};
|
|
uint32_t reserved;
|
|
uint32_t debug_vmid;
|
|
uint64_t process_context_addr;
|
|
uint64_t page_table_base_addr;
|
|
uint64_t process_va_start;
|
|
uint64_t process_va_end;
|
|
uint32_t gds_base;
|
|
uint32_t gds_size;
|
|
uint32_t gws_base;
|
|
uint32_t gws_size;
|
|
uint32_t oa_mask;
|
|
|
|
/* output addr of the acquired vmid value */
|
|
uint64_t output_addr;
|
|
};
|
|
|
|
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
|
|
};
|
|
|
|
enum MESAPI_MISC_OPCODE {
|
|
MESAPI_MISC__WRITE_REG,
|
|
MESAPI_MISC__INV_GART,
|
|
MESAPI_MISC__QUERY_STATUS,
|
|
MESAPI_MISC__READ_REG,
|
|
MESAPI_MISC__WAIT_REG_MEM,
|
|
MESAPI_MISC__SET_SHADER_DEBUGGER,
|
|
MESAPI_MISC__MAX,
|
|
};
|
|
|
|
enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
|
|
|
|
struct WRITE_REG {
|
|
uint32_t reg_offset;
|
|
uint32_t reg_value;
|
|
};
|
|
|
|
struct READ_REG {
|
|
uint32_t reg_offset;
|
|
uint64_t buffer_addr;
|
|
};
|
|
|
|
enum WRM_OPERATION {
|
|
WRM_OPERATION__WAIT_REG_MEM,
|
|
WRM_OPERATION__WR_WAIT_WR_REG,
|
|
WRM_OPERATION__MAX,
|
|
};
|
|
|
|
struct WAIT_REG_MEM {
|
|
enum WRM_OPERATION op;
|
|
uint32_t reference;
|
|
uint32_t mask;
|
|
uint32_t reg_offset1;
|
|
uint32_t reg_offset2;
|
|
};
|
|
|
|
struct INV_GART {
|
|
uint64_t inv_range_va_start;
|
|
uint64_t inv_range_size;
|
|
};
|
|
|
|
struct QUERY_STATUS {
|
|
uint32_t context_id;
|
|
};
|
|
|
|
struct SET_SHADER_DEBUGGER {
|
|
uint64_t process_context_addr;
|
|
union {
|
|
struct {
|
|
uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */
|
|
uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
|
|
uint32_t reserved : 30;
|
|
};
|
|
uint32_t u32all;
|
|
} flags;
|
|
uint32_t spi_gdbg_per_vmid_cntl;
|
|
uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
|
|
uint32_t trap_en;
|
|
};
|
|
|
|
union MESAPI__MISC {
|
|
struct {
|
|
union MES_API_HEADER header;
|
|
enum MESAPI_MISC_OPCODE opcode;
|
|
struct MES_API_STATUS api_status;
|
|
|
|
union {
|
|
struct WRITE_REG write_reg;
|
|
struct INV_GART inv_gart;
|
|
struct QUERY_STATUS query_status;
|
|
struct READ_REG read_reg;
|
|
struct WAIT_REG_MEM wait_reg_mem;
|
|
struct SET_SHADER_DEBUGGER set_shader_debugger;
|
|
enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
|
|
|
|
uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
|
|
};
|
|
};
|
|
|
|
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
|
|
};
|
|
|
|
union MESAPI__UPDATE_ROOT_PAGE_TABLE {
|
|
struct {
|
|
union MES_API_HEADER header;
|
|
uint64_t page_table_base_addr;
|
|
uint64_t process_context_addr;
|
|
struct MES_API_STATUS api_status;
|
|
};
|
|
|
|
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
|
|
};
|
|
|
|
union MESAPI_AMD_LOG {
|
|
struct {
|
|
union MES_API_HEADER header;
|
|
uint64_t p_buffer_memory;
|
|
uint64_t p_buffer_size_used;
|
|
struct MES_API_STATUS api_status;
|
|
};
|
|
|
|
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
|
|
};
|
|
|
|
#pragma pack(pop)
|
|
#endif
|