608 lines
16 KiB
C
608 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2006 Intel Corporation
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*/
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#ifndef _INTEL_BIOS_H_
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#define _INTEL_BIOS_H_
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struct drm_device;
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struct vbt_header {
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u8 signature[20]; /**< Always starts with 'VBT$' */
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u16 version; /**< decimal */
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u16 header_size; /**< in bytes */
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u16 vbt_size; /**< in bytes */
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u8 vbt_checksum;
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u8 reserved0;
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u32 bdb_offset; /**< from beginning of VBT */
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u32 aim_offset[4]; /**< from beginning of VBT */
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} __packed;
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struct bdb_header {
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u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
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u16 version; /**< decimal */
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u16 header_size; /**< in bytes */
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u16 bdb_size; /**< in bytes */
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};
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/* strictly speaking, this is a "skip" block, but it has interesting info */
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struct vbios_data {
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u8 type; /* 0 == desktop, 1 == mobile */
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u8 relstage;
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u8 chipset;
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u8 lvds_present:1;
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u8 tv_present:1;
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u8 rsvd2:6; /* finish byte */
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u8 rsvd3[4];
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u8 signon[155];
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u8 copyright[61];
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u16 code_segment;
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u8 dos_boot_mode;
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u8 bandwidth_percent;
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u8 rsvd4; /* popup memory size */
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u8 resize_pci_bios;
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u8 rsvd5; /* is crt already on ddc2 */
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} __packed;
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/*
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* There are several types of BIOS data blocks (BDBs), each block has
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* an ID and size in the first 3 bytes (ID in first, size in next 2).
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* Known types are listed below.
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*/
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#define BDB_GENERAL_FEATURES 1
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#define BDB_GENERAL_DEFINITIONS 2
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#define BDB_OLD_TOGGLE_LIST 3
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#define BDB_MODE_SUPPORT_LIST 4
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#define BDB_GENERIC_MODE_TABLE 5
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#define BDB_EXT_MMIO_REGS 6
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#define BDB_SWF_IO 7
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#define BDB_SWF_MMIO 8
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#define BDB_DOT_CLOCK_TABLE 9
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#define BDB_MODE_REMOVAL_TABLE 10
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#define BDB_CHILD_DEVICE_TABLE 11
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#define BDB_DRIVER_FEATURES 12
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#define BDB_DRIVER_PERSISTENCE 13
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#define BDB_EXT_TABLE_PTRS 14
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#define BDB_DOT_CLOCK_OVERRIDE 15
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#define BDB_DISPLAY_SELECT 16
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/* 17 rsvd */
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#define BDB_DRIVER_ROTATION 18
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#define BDB_DISPLAY_REMOVE 19
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#define BDB_OEM_CUSTOM 20
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#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
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#define BDB_SDVO_LVDS_OPTIONS 22
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#define BDB_SDVO_PANEL_DTDS 23
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#define BDB_SDVO_LVDS_PNP_IDS 24
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#define BDB_SDVO_LVDS_POWER_SEQ 25
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#define BDB_TV_OPTIONS 26
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#define BDB_EDP 27
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#define BDB_LVDS_OPTIONS 40
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#define BDB_LVDS_LFP_DATA_PTRS 41
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#define BDB_LVDS_LFP_DATA 42
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#define BDB_LVDS_BACKLIGHT 43
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#define BDB_LVDS_POWER 44
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#define BDB_SKIP 254 /* VBIOS private block, ignore */
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struct bdb_general_features {
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/* bits 1 */
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u8 panel_fitting:2;
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u8 flexaim:1;
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u8 msg_enable:1;
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u8 clear_screen:3;
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u8 color_flip:1;
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/* bits 2 */
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u8 download_ext_vbt:1;
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u8 enable_ssc:1;
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u8 ssc_freq:1;
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u8 enable_lfp_on_override:1;
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u8 disable_ssc_ddt:1;
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u8 rsvd8:3; /* finish byte */
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/* bits 3 */
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u8 disable_smooth_vision:1;
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u8 single_dvi:1;
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u8 rsvd9:6; /* finish byte */
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/* bits 4 */
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u8 legacy_monitor_detect;
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/* bits 5 */
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u8 int_crt_support:1;
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u8 int_tv_support:1;
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u8 int_efp_support:1;
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u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
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u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
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u8 rsvd11:3; /* finish byte */
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} __packed;
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/* pre-915 */
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#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
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#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
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#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
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#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
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/* Pre 915 */
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#define DEVICE_TYPE_NONE 0x00
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#define DEVICE_TYPE_CRT 0x01
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#define DEVICE_TYPE_TV 0x09
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#define DEVICE_TYPE_EFP 0x12
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#define DEVICE_TYPE_LFP 0x22
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/* On 915+ */
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#define DEVICE_TYPE_CRT_DPMS 0x6001
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#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
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#define DEVICE_TYPE_TV_COMPOSITE 0x0209
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#define DEVICE_TYPE_TV_MACROVISION 0x0289
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#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
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#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
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#define DEVICE_TYPE_TV_SCART 0x0209
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#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
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#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
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#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
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#define DEVICE_TYPE_EFP_DVI_I 0x6053
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#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
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#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
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#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
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#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
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#define DEVICE_TYPE_LFP_PANELLINK 0x5012
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#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
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#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
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#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
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#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
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#define DEVICE_CFG_NONE 0x00
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#define DEVICE_CFG_12BIT_DVOB 0x01
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#define DEVICE_CFG_12BIT_DVOC 0x02
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#define DEVICE_CFG_24BIT_DVOBC 0x09
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#define DEVICE_CFG_24BIT_DVOCB 0x0a
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#define DEVICE_CFG_DUAL_DVOB 0x11
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#define DEVICE_CFG_DUAL_DVOC 0x12
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#define DEVICE_CFG_DUAL_DVOBC 0x13
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#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
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#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
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#define DEVICE_WIRE_NONE 0x00
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#define DEVICE_WIRE_DVOB 0x01
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#define DEVICE_WIRE_DVOC 0x02
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#define DEVICE_WIRE_DVOBC 0x03
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#define DEVICE_WIRE_DVOBB 0x05
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#define DEVICE_WIRE_DVOCC 0x06
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#define DEVICE_WIRE_DVOB_MASTER 0x0d
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#define DEVICE_WIRE_DVOC_MASTER 0x0e
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#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
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#define DEVICE_PORT_DVOB 0x01
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#define DEVICE_PORT_DVOC 0x02
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struct child_device_config {
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u16 handle;
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u16 device_type;
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u8 device_id[10]; /* ascii string */
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u16 addin_offset;
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u8 dvo_port; /* See Device_PORT_* above */
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u8 i2c_pin;
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u8 slave_addr;
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u8 ddc_pin;
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u16 edid_ptr;
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u8 dvo_cfg; /* See DEVICE_CFG_* above */
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u8 dvo2_port;
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u8 i2c2_pin;
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u8 slave2_addr;
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u8 ddc2_pin;
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u8 capabilities;
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u8 dvo_wiring;/* See DEVICE_WIRE_* above */
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u8 dvo2_wiring;
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u16 extended_type;
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u8 dvo_function;
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} __packed;
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struct bdb_general_definitions {
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/* DDC GPIO */
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u8 crt_ddc_gmbus_pin;
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/* DPMS bits */
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u8 dpms_acpi:1;
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u8 skip_boot_crt_detect:1;
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u8 dpms_aim:1;
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u8 rsvd1:5; /* finish byte */
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/* boot device bits */
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u8 boot_display[2];
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u8 child_dev_size;
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/*
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* Device info:
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* If TV is present, it'll be at devices[0].
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* LVDS will be next, either devices[0] or [1], if present.
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* On some platforms the number of device is 6. But could be as few as
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* 4 if both TV and LVDS are missing.
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* And the device num is related with the size of general definition
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* block. It is obtained by using the following formula:
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* number = (block_size - sizeof(bdb_general_definitions))/
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* sizeof(child_device_config);
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*/
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struct child_device_config devices[];
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};
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struct bdb_lvds_options {
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u8 panel_type;
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u8 rsvd1;
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/* LVDS capabilities, stored in a dword */
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u8 pfit_mode:2;
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u8 pfit_text_mode_enhanced:1;
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u8 pfit_gfx_mode_enhanced:1;
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u8 pfit_ratio_auto:1;
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u8 pixel_dither:1;
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u8 lvds_edid:1;
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u8 rsvd2:1;
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u8 rsvd4;
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} __packed;
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struct bdb_lvds_backlight {
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u8 type:2;
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u8 pol:1;
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u8 gpio:3;
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u8 gmbus:2;
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u16 freq;
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u8 minbrightness;
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u8 i2caddr;
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u8 brightnesscmd;
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/*FIXME: more...*/
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} __packed;
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/* LFP pointer table contains entries to the struct below */
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struct bdb_lvds_lfp_data_ptr {
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u16 fp_timing_offset; /* offsets are from start of bdb */
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u8 fp_table_size;
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u16 dvo_timing_offset;
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u8 dvo_table_size;
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u16 panel_pnp_id_offset;
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u8 pnp_table_size;
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} __packed;
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struct bdb_lvds_lfp_data_ptrs {
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u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
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struct bdb_lvds_lfp_data_ptr ptr[16];
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} __packed;
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/* LFP data has 3 blocks per entry */
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struct lvds_fp_timing {
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u16 x_res;
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u16 y_res;
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u32 lvds_reg;
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u32 lvds_reg_val;
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u32 pp_on_reg;
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u32 pp_on_reg_val;
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u32 pp_off_reg;
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u32 pp_off_reg_val;
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u32 pp_cycle_reg;
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u32 pp_cycle_reg_val;
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u32 pfit_reg;
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u32 pfit_reg_val;
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u16 terminator;
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} __packed;
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struct lvds_dvo_timing {
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u16 clock; /**< In 10khz */
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_off_lo;
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u8 hsync_pulse_width;
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u8 vsync_pulse_width:4;
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u8 vsync_off:4;
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u8 rsvd0:6;
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u8 hsync_off_hi:2;
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u8 h_image;
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u8 v_image;
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u8 max_hv;
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u8 h_border;
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u8 v_border;
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u8 rsvd1:3;
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u8 digital:2;
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u8 vsync_positive:1;
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u8 hsync_positive:1;
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u8 rsvd2:1;
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} __packed;
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struct lvds_pnp_id {
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u16 mfg_name;
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u16 product_code;
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u32 serial;
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u8 mfg_week;
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u8 mfg_year;
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} __packed;
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struct bdb_lvds_lfp_data_entry {
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struct lvds_fp_timing fp_timing;
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struct lvds_dvo_timing dvo_timing;
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struct lvds_pnp_id pnp_id;
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} __packed;
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struct bdb_lvds_lfp_data {
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struct bdb_lvds_lfp_data_entry data[16];
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} __packed;
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struct aimdb_header {
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char signature[16];
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char oem_device[20];
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u16 aimdb_version;
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u16 aimdb_header_size;
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u16 aimdb_size;
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} __packed;
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struct aimdb_block {
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u8 aimdb_id;
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u16 aimdb_size;
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} __packed;
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struct vch_panel_data {
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u16 fp_timing_offset;
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u8 fp_timing_size;
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u16 dvo_timing_offset;
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u8 dvo_timing_size;
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u16 text_fitting_offset;
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u8 text_fitting_size;
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u16 graphics_fitting_offset;
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u8 graphics_fitting_size;
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} __packed;
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struct vch_bdb_22 {
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struct aimdb_block aimdb_block;
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struct vch_panel_data panels[16];
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} __packed;
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struct bdb_sdvo_lvds_options {
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u8 panel_backlight;
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u8 h40_set_panel_type;
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u8 panel_type;
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u8 ssc_clk_freq;
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u16 als_low_trip;
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u16 als_high_trip;
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u8 sclalarcoeff_tab_row_num;
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u8 sclalarcoeff_tab_row_size;
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u8 coefficient[8];
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u8 panel_misc_bits_1;
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u8 panel_misc_bits_2;
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u8 panel_misc_bits_3;
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u8 panel_misc_bits_4;
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} __packed;
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#define BDB_DRIVER_FEATURE_NO_LVDS 0
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#define BDB_DRIVER_FEATURE_INT_LVDS 1
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#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
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#define BDB_DRIVER_FEATURE_EDP 3
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struct bdb_driver_features {
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u8 boot_dev_algorithm:1;
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u8 block_display_switch:1;
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u8 allow_display_switch:1;
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u8 hotplug_dvo:1;
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u8 dual_view_zoom:1;
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u8 int15h_hook:1;
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u8 sprite_in_clone:1;
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u8 primary_lfp_id:1;
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u16 boot_mode_x;
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u16 boot_mode_y;
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u8 boot_mode_bpp;
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u8 boot_mode_refresh;
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u16 enable_lfp_primary:1;
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u16 selective_mode_pruning:1;
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u16 dual_frequency:1;
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u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
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u16 nt_clone_support:1;
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u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
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u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
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u16 cui_aspect_scaling:1;
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u16 preserve_aspect_ratio:1;
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u16 sdvo_device_power_down:1;
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u16 crt_hotplug:1;
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u16 lvds_config:2;
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u16 tv_hotplug:1;
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u16 hdmi_config:2;
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u8 static_display:1;
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u8 reserved2:7;
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u16 legacy_crt_max_x;
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u16 legacy_crt_max_y;
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u8 legacy_crt_max_refresh;
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u8 hdmi_termination;
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u8 custom_vbt_version;
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} __packed;
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#define EDP_18BPP 0
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#define EDP_24BPP 1
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#define EDP_30BPP 2
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#define EDP_RATE_1_62 0
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#define EDP_RATE_2_7 1
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#define EDP_LANE_1 0
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#define EDP_LANE_2 1
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#define EDP_LANE_4 3
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#define EDP_PREEMPHASIS_NONE 0
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#define EDP_PREEMPHASIS_3_5dB 1
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#define EDP_PREEMPHASIS_6dB 2
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#define EDP_PREEMPHASIS_9_5dB 3
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#define EDP_VSWING_0_4V 0
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#define EDP_VSWING_0_6V 1
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#define EDP_VSWING_0_8V 2
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#define EDP_VSWING_1_2V 3
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struct edp_power_seq {
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u16 t1_t3;
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u16 t8;
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u16 t9;
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u16 t10;
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u16 t11_t12;
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} __attribute__ ((packed));
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struct edp_link_params {
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u8 rate:4;
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u8 lanes:4;
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u8 preemphasis:4;
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u8 vswing:4;
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} __attribute__ ((packed));
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struct bdb_edp {
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struct edp_power_seq power_seqs[16];
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u32 color_depth;
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u32 sdrrs_msa_timing_delay;
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struct edp_link_params link_params[16];
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} __attribute__ ((packed));
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extern int psb_intel_init_bios(struct drm_device *dev);
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extern void psb_intel_destroy_bios(struct drm_device *dev);
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/*
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* Driver<->VBIOS interaction occurs through scratch bits in
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* GR18 & SWF*.
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*/
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/* GR18 bits are set on display switch and hotkey events */
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#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
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#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
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#define GR18_HK_NONE (0x0<<3)
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#define GR18_HK_LFP_STRETCH (0x1<<3)
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#define GR18_HK_TOGGLE_DISP (0x2<<3)
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#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
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#define GR18_HK_POPUP_DISABLED (0x6<<3)
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#define GR18_HK_POPUP_ENABLED (0x7<<3)
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#define GR18_HK_PFIT (0x8<<3)
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#define GR18_HK_APM_CHANGE (0xa<<3)
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#define GR18_HK_MULTIPLE (0xc<<3)
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#define GR18_USER_INT_EN (1<<2)
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#define GR18_A0000_FLUSH_EN (1<<1)
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#define GR18_SMM_EN (1<<0)
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/* Set by driver, cleared by VBIOS */
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#define SWF00_YRES_SHIFT 16
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#define SWF00_XRES_SHIFT 0
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#define SWF00_RES_MASK 0xffff
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/* Set by VBIOS at boot time and driver at runtime */
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#define SWF01_TV2_FORMAT_SHIFT 8
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#define SWF01_TV1_FORMAT_SHIFT 0
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#define SWF01_TV_FORMAT_MASK 0xffff
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#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
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#define SWF10_GTT_OVERRIDE_EN (1<<28)
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#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
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#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
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#define SWF10_OLD_TOGGLE 0x0
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#define SWF10_TOGGLE_LIST_1 0x1
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#define SWF10_TOGGLE_LIST_2 0x2
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#define SWF10_TOGGLE_LIST_3 0x3
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#define SWF10_TOGGLE_LIST_4 0x4
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#define SWF10_PANNING_EN (1<<23)
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#define SWF10_DRIVER_LOADED (1<<22)
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#define SWF10_EXTENDED_DESKTOP (1<<21)
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#define SWF10_EXCLUSIVE_MODE (1<<20)
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#define SWF10_OVERLAY_EN (1<<19)
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#define SWF10_PLANEB_HOLDOFF (1<<18)
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#define SWF10_PLANEA_HOLDOFF (1<<17)
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#define SWF10_VGA_HOLDOFF (1<<16)
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#define SWF10_ACTIVE_DISP_MASK 0xffff
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#define SWF10_PIPEB_LFP2 (1<<15)
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#define SWF10_PIPEB_EFP2 (1<<14)
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#define SWF10_PIPEB_TV2 (1<<13)
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#define SWF10_PIPEB_CRT2 (1<<12)
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#define SWF10_PIPEB_LFP (1<<11)
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#define SWF10_PIPEB_EFP (1<<10)
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#define SWF10_PIPEB_TV (1<<9)
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#define SWF10_PIPEB_CRT (1<<8)
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#define SWF10_PIPEA_LFP2 (1<<7)
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#define SWF10_PIPEA_EFP2 (1<<6)
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#define SWF10_PIPEA_TV2 (1<<5)
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#define SWF10_PIPEA_CRT2 (1<<4)
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#define SWF10_PIPEA_LFP (1<<3)
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#define SWF10_PIPEA_EFP (1<<2)
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#define SWF10_PIPEA_TV (1<<1)
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#define SWF10_PIPEA_CRT (1<<0)
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#define SWF11_MEMORY_SIZE_SHIFT 16
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#define SWF11_SV_TEST_EN (1<<15)
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#define SWF11_IS_AGP (1<<14)
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#define SWF11_DISPLAY_HOLDOFF (1<<13)
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#define SWF11_DPMS_REDUCED (1<<12)
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#define SWF11_IS_VBE_MODE (1<<11)
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#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
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#define SWF11_DPMS_MASK 0x07
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#define SWF11_DPMS_OFF (1<<2)
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#define SWF11_DPMS_SUSPEND (1<<1)
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#define SWF11_DPMS_STANDBY (1<<0)
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#define SWF11_DPMS_ON 0
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#define SWF14_GFX_PFIT_EN (1<<31)
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#define SWF14_TEXT_PFIT_EN (1<<30)
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#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
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#define SWF14_POPUP_EN (1<<28)
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#define SWF14_DISPLAY_HOLDOFF (1<<27)
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#define SWF14_DISP_DETECT_EN (1<<26)
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#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
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#define SWF14_DRIVER_STATUS (1<<24)
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#define SWF14_OS_TYPE_WIN9X (1<<23)
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#define SWF14_OS_TYPE_WINNT (1<<22)
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/* 21:19 rsvd */
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#define SWF14_PM_TYPE_MASK 0x00070000
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#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
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#define SWF14_PM_ACPI (0x3 << 16)
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#define SWF14_PM_APM_12 (0x2 << 16)
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#define SWF14_PM_APM_11 (0x1 << 16)
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#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
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/* if GR18 indicates a display switch */
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#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
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#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
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#define SWF14_DS_PIPEB_TV2_EN (1<<13)
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#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
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#define SWF14_DS_PIPEB_LFP_EN (1<<11)
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#define SWF14_DS_PIPEB_EFP_EN (1<<10)
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#define SWF14_DS_PIPEB_TV_EN (1<<9)
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#define SWF14_DS_PIPEB_CRT_EN (1<<8)
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#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
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#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
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#define SWF14_DS_PIPEA_TV2_EN (1<<5)
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#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
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#define SWF14_DS_PIPEA_LFP_EN (1<<3)
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#define SWF14_DS_PIPEA_EFP_EN (1<<2)
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#define SWF14_DS_PIPEA_TV_EN (1<<1)
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#define SWF14_DS_PIPEA_CRT_EN (1<<0)
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/* if GR18 indicates a panel fitting request */
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#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
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/* if GR18 indicates an APM change request */
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#define SWF14_APM_HIBERNATE 0x4
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#define SWF14_APM_SUSPEND 0x3
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#define SWF14_APM_STANDBY 0x1
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#define SWF14_APM_RESTORE 0x0
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/* Add the device class for LFP, TV, HDMI */
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#define DEVICE_TYPE_INT_LFP 0x1022
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#define DEVICE_TYPE_INT_TV 0x1009
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#define DEVICE_TYPE_HDMI 0x60D2
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#define DEVICE_TYPE_DP 0x68C6
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#define DEVICE_TYPE_eDP 0x78C6
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/* define the DVO port for HDMI output type */
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#define DVO_B 1
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#define DVO_C 2
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#define DVO_D 3
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/* define the PORT for DP output type */
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#define PORT_IDPB 7
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#define PORT_IDPC 8
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#define PORT_IDPD 9
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#endif /* _INTEL_BIOS_H_ */
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