333 lines
8.1 KiB
C
333 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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**************************************************************************/
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/* TODO
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* - Split functions by vbt type
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* - Make them all take drm_device
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* - Check ioremap failures
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*/
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#include <drm/drm.h>
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#include "mid_bios.h"
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#include "psb_drv.h"
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static void mid_get_fuse_settings(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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struct pci_dev *pci_root =
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pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
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0, 0);
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uint32_t fuse_value = 0;
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uint32_t fuse_value_tmp = 0;
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#define FB_REG06 0xD0810600
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#define FB_MIPI_DISABLE (1 << 11)
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#define FB_REG09 0xD0810900
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#define FB_SKU_MASK 0x7000
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#define FB_SKU_SHIFT 12
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#define FB_SKU_100 0
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#define FB_SKU_100L 1
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#define FB_SKU_83 2
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if (pci_root == NULL) {
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WARN_ON(1);
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return;
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}
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pci_write_config_dword(pci_root, 0xD0, FB_REG06);
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pci_read_config_dword(pci_root, 0xD4, &fuse_value);
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/* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
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if (IS_MRST(dev))
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dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
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DRM_INFO("internal display is %s\n",
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dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
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/* Prevent runtime suspend at start*/
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if (dev_priv->iLVDS_enable) {
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dev_priv->is_lvds_on = true;
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dev_priv->is_mipi_on = false;
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} else {
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dev_priv->is_mipi_on = true;
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dev_priv->is_lvds_on = false;
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}
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dev_priv->video_device_fuse = fuse_value;
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pci_write_config_dword(pci_root, 0xD0, FB_REG09);
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pci_read_config_dword(pci_root, 0xD4, &fuse_value);
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dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
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fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
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dev_priv->fuse_reg_value = fuse_value;
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switch (fuse_value_tmp) {
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case FB_SKU_100:
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dev_priv->core_freq = 200;
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break;
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case FB_SKU_100L:
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dev_priv->core_freq = 100;
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break;
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case FB_SKU_83:
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dev_priv->core_freq = 166;
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break;
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default:
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dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
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fuse_value_tmp);
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dev_priv->core_freq = 0;
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}
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dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
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pci_dev_put(pci_root);
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}
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/*
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* Get the revison ID, B0:D2:F0;0x08
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*/
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static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
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{
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uint32_t platform_rev_id = 0;
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struct pci_dev *pdev = to_pci_dev(dev_priv->dev.dev);
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int domain = pci_domain_nr(pdev->bus);
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struct pci_dev *pci_gfx_root =
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pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
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if (pci_gfx_root == NULL) {
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WARN_ON(1);
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return;
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}
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pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
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dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
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pci_dev_put(pci_gfx_root);
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dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id);
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}
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struct mid_vbt_header {
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u32 signature;
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u8 revision;
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} __packed;
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/* The same for r0 and r1 */
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struct vbt_r0 {
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struct mid_vbt_header vbt_header;
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u8 size;
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u8 checksum;
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} __packed;
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struct vbt_r10 {
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struct mid_vbt_header vbt_header;
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u8 checksum;
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u16 size;
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u8 panel_count;
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u8 primary_panel_idx;
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u8 secondary_panel_idx;
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u8 __reserved[5];
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} __packed;
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static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
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{
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void __iomem *vbt_virtual;
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vbt_virtual = ioremap(addr, sizeof(*vbt));
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if (vbt_virtual == NULL)
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return -1;
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memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
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iounmap(vbt_virtual);
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return 0;
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}
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static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
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{
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void __iomem *vbt_virtual;
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vbt_virtual = ioremap(addr, sizeof(*vbt));
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if (!vbt_virtual)
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return -1;
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memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
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iounmap(vbt_virtual);
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return 0;
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}
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static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
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{
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struct vbt_r0 vbt;
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void __iomem *gct_virtual;
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struct gct_r0 gct;
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u8 bpi;
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if (read_vbt_r0(addr, &vbt))
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return -1;
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gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
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if (!gct_virtual)
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return -1;
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memcpy_fromio(&gct, gct_virtual, sizeof(gct));
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iounmap(gct_virtual);
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bpi = gct.PD.BootPanelIndex;
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dev_priv->gct_data.bpi = bpi;
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dev_priv->gct_data.pt = gct.PD.PanelType;
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dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
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dev_priv->gct_data.Panel_Port_Control =
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gct.panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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gct.panel[bpi].Panel_MIPI_Display_Descriptor;
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return 0;
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}
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static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
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{
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struct vbt_r0 vbt;
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void __iomem *gct_virtual;
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struct gct_r1 gct;
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u8 bpi;
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if (read_vbt_r0(addr, &vbt))
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return -1;
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gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
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if (!gct_virtual)
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return -1;
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memcpy_fromio(&gct, gct_virtual, sizeof(gct));
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iounmap(gct_virtual);
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bpi = gct.PD.BootPanelIndex;
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dev_priv->gct_data.bpi = bpi;
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dev_priv->gct_data.pt = gct.PD.PanelType;
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dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
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dev_priv->gct_data.Panel_Port_Control =
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gct.panel[bpi].Panel_Port_Control;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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gct.panel[bpi].Panel_MIPI_Display_Descriptor;
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return 0;
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}
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static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
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{
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struct vbt_r10 vbt;
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void __iomem *gct_virtual;
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struct gct_r10 *gct;
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struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
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struct gct_r10_timing_info *ti;
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int ret = -1;
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if (read_vbt_r10(addr, &vbt))
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return -1;
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gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
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if (!gct)
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return -ENOMEM;
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gct_virtual = ioremap(addr + sizeof(vbt),
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sizeof(*gct) * vbt.panel_count);
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if (!gct_virtual)
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goto out;
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memcpy_fromio(gct, gct_virtual, sizeof(*gct));
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iounmap(gct_virtual);
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dev_priv->gct_data.bpi = vbt.primary_panel_idx;
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dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
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gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
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ti = &gct[vbt.primary_panel_idx].DTD;
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dp_ti->pixel_clock = ti->pixel_clock;
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dp_ti->hactive_hi = ti->hactive_hi;
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dp_ti->hactive_lo = ti->hactive_lo;
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dp_ti->hblank_hi = ti->hblank_hi;
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dp_ti->hblank_lo = ti->hblank_lo;
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dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
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dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
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dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
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dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
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dp_ti->vactive_hi = ti->vactive_hi;
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dp_ti->vactive_lo = ti->vactive_lo;
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dp_ti->vblank_hi = ti->vblank_hi;
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dp_ti->vblank_lo = ti->vblank_lo;
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dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
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dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
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dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
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dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
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ret = 0;
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out:
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kfree(gct);
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return ret;
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}
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static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
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{
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struct drm_device *dev = &dev_priv->dev;
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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u32 addr;
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u8 __iomem *vbt_virtual;
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struct mid_vbt_header vbt_header;
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struct pci_dev *pci_gfx_root =
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pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
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0, PCI_DEVFN(2, 0));
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int ret = -1;
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/* Get the address of the platform config vbt */
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pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
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pci_dev_put(pci_gfx_root);
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dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
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if (!addr)
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goto out;
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/* get the virtual address of the vbt */
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vbt_virtual = ioremap(addr, sizeof(vbt_header));
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if (!vbt_virtual)
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goto out;
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memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
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iounmap(vbt_virtual);
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if (memcmp(&vbt_header.signature, "$GCT", 4))
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goto out;
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dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
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switch (vbt_header.revision) {
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case 0x00:
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ret = mid_get_vbt_data_r0(dev_priv, addr);
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break;
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case 0x01:
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ret = mid_get_vbt_data_r1(dev_priv, addr);
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break;
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case 0x10:
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ret = mid_get_vbt_data_r10(dev_priv, addr);
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break;
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default:
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dev_err(dev->dev, "Unknown revision of GCT!\n");
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}
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out:
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if (ret)
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dev_err(dev->dev, "Unable to read GCT!");
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else
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dev_priv->has_gct = true;
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}
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int mid_chip_setup(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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mid_get_fuse_settings(dev);
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mid_get_vbt_data(dev_priv);
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mid_get_pci_revID(dev_priv);
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return 0;
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}
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