638 lines
19 KiB
C
638 lines
19 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "head.h"
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#include "base.h"
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#include "core.h"
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#include "curs.h"
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#include "ovly.h"
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#include "crc.h"
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#include <nvif/class.h>
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#include <nvif/event.h>
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#include <nvif/cl0046.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_vblank.h>
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#include "nouveau_connector.h"
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void
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nv50_head_flush_clr(struct nv50_head *head,
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struct nv50_head_atom *asyh, bool flush)
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{
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union nv50_head_atom_mask clr = {
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.mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
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};
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if (clr.crc) nv50_crc_atomic_clr(head);
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if (clr.olut) head->func->olut_clr(head);
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if (clr.core) head->func->core_clr(head);
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if (clr.curs) head->func->curs_clr(head);
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}
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void
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nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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if (asyh->set.curs ) head->func->curs_set(head, asyh);
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if (asyh->set.olut ) {
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asyh->olut.offset = nv50_lut_load(&head->olut,
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asyh->olut.buffer,
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asyh->state.gamma_lut,
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asyh->olut.load);
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head->func->olut_set(head, asyh);
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}
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}
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void
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nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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if (asyh->set.view ) head->func->view (head, asyh);
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if (asyh->set.mode ) head->func->mode (head, asyh);
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if (asyh->set.core ) head->func->core_set(head, asyh);
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if (asyh->set.base ) head->func->base (head, asyh);
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if (asyh->set.ovly ) head->func->ovly (head, asyh);
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if (asyh->set.dither ) head->func->dither (head, asyh);
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if (asyh->set.procamp) head->func->procamp (head, asyh);
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if (asyh->set.crc ) nv50_crc_atomic_set (head, asyh);
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if (asyh->set.or ) head->func->or (head, asyh);
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}
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static void
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nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
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struct nv50_head_atom *asyh,
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struct nouveau_conn_atom *asyc)
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{
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const int vib = asyc->procamp.color_vibrance - 100;
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const int hue = asyc->procamp.vibrant_hue - 90;
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const int adj = (vib > 0) ? 50 : 0;
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asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
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asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
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asyh->set.procamp = true;
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}
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static void
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nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
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struct nv50_head_atom *asyh,
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struct nouveau_conn_atom *asyc)
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{
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u32 mode = 0x00;
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if (asyc->dither.mode) {
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if (asyc->dither.mode == DITHERING_MODE_AUTO) {
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if (asyh->base.depth > asyh->or.bpc * 3)
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mode = DITHERING_MODE_DYNAMIC2X2;
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} else {
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mode = asyc->dither.mode;
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}
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if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
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if (asyh->or.bpc >= 8)
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mode |= DITHERING_DEPTH_8BPC;
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} else {
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mode |= asyc->dither.depth;
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}
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}
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asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
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asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
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asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
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asyh->set.dither = true;
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}
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static void
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nv50_head_atomic_check_view(struct nv50_head_atom *armh,
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struct nv50_head_atom *asyh,
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struct nouveau_conn_atom *asyc)
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{
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struct drm_connector *connector = asyc->state.connector;
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struct drm_display_mode *omode = &asyh->state.adjusted_mode;
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struct drm_display_mode *umode = &asyh->state.mode;
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int mode = asyc->scaler.mode;
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struct edid *edid;
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int umode_vdisplay, omode_hdisplay, omode_vdisplay;
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if (connector->edid_blob_ptr)
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edid = (struct edid *)connector->edid_blob_ptr->data;
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else
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edid = NULL;
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if (!asyc->scaler.full) {
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if (mode == DRM_MODE_SCALE_NONE)
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omode = umode;
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} else {
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/* Non-EDID LVDS/eDP mode. */
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mode = DRM_MODE_SCALE_FULLSCREEN;
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}
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/* For the user-specified mode, we must ignore doublescan and
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* the like, but honor frame packing.
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*/
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umode_vdisplay = umode->vdisplay;
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if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
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umode_vdisplay += umode->vtotal;
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asyh->view.iW = umode->hdisplay;
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asyh->view.iH = umode_vdisplay;
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/* For the output mode, we can just use the stock helper. */
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drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
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asyh->view.oW = omode_hdisplay;
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asyh->view.oH = omode_vdisplay;
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/* Add overscan compensation if necessary, will keep the aspect
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* ratio the same as the backend mode unless overridden by the
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* user setting both hborder and vborder properties.
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*/
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if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
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(asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
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drm_detect_hdmi_monitor(edid)))) {
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u32 bX = asyc->scaler.underscan.hborder;
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u32 bY = asyc->scaler.underscan.vborder;
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u32 r = (asyh->view.oH << 19) / asyh->view.oW;
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if (bX) {
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asyh->view.oW -= (bX * 2);
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if (bY) asyh->view.oH -= (bY * 2);
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else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
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} else {
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asyh->view.oW -= (asyh->view.oW >> 4) + 32;
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if (bY) asyh->view.oH -= (bY * 2);
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else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
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}
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}
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/* Handle CENTER/ASPECT scaling, taking into account the areas
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* removed already for overscan compensation.
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*/
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switch (mode) {
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case DRM_MODE_SCALE_CENTER:
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/* NOTE: This will cause scaling when the input is
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* larger than the output.
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*/
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asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
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asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
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break;
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case DRM_MODE_SCALE_ASPECT:
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/* Determine whether the scaling should be on width or on
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* height. This is done by comparing the aspect ratios of the
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* sizes. If the output AR is larger than input AR, that means
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* we want to change the width (letterboxed on the
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* left/right), otherwise on the height (letterboxed on the
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* top/bottom).
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*
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* E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
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* screen will have letterboxes on the left/right. However a
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* 16:9 (1.777) AR image on that same screen will have
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* letterboxes on the top/bottom.
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*
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* inputAR = iW / iH; outputAR = oW / oH
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* outputAR > inputAR is equivalent to oW * iH > iW * oH
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*/
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if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
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/* Recompute output width, i.e. left/right letterbox */
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u32 r = (asyh->view.iW << 19) / asyh->view.iH;
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asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
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} else {
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/* Recompute output height, i.e. top/bottom letterbox */
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u32 r = (asyh->view.iH << 19) / asyh->view.iW;
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asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
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}
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break;
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default:
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break;
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}
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asyh->set.view = true;
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}
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static int
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nv50_head_atomic_check_lut(struct nv50_head *head,
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struct nv50_head_atom *asyh)
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{
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struct drm_device *dev = head->base.base.dev;
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struct drm_crtc *crtc = &head->base.base;
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struct nv50_disp *disp = nv50_disp(dev);
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct drm_property_blob *olut = asyh->state.gamma_lut,
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*ilut = asyh->state.degamma_lut;
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int size;
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/* Ensure that the ilut is valid */
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if (ilut) {
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size = drm_color_lut_size(ilut);
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if (!head->func->ilut_check(size)) {
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NV_ATOMIC(drm, "Invalid size %d for degamma on [CRTC:%d:%s]\n",
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size, crtc->base.id, crtc->name);
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return -EINVAL;
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}
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}
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/* Determine whether core output LUT should be enabled. */
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if (olut) {
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/* Check if any window(s) have stolen the core output LUT
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* to as an input LUT for legacy gamma + I8 colour format.
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*/
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if (asyh->wndw.olut) {
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/* If any window has stolen the core output LUT,
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* all of them must.
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*/
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if (asyh->wndw.olut != asyh->wndw.mask)
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return -EINVAL;
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olut = NULL;
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}
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}
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if (!olut) {
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if (!head->func->olut_identity) {
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asyh->olut.handle = 0;
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return 0;
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}
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size = 0;
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} else {
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size = drm_color_lut_size(olut);
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}
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if (!head->func->olut(head, asyh, size)) {
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NV_ATOMIC(drm, "Invalid size %d for gamma on [CRTC:%d:%s]\n",
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size, crtc->base.id, crtc->name);
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return -EINVAL;
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}
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asyh->olut.handle = disp->core->chan.vram.handle;
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asyh->olut.buffer = !asyh->olut.buffer;
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return 0;
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}
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static void
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nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct drm_display_mode *mode = &asyh->state.adjusted_mode;
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struct nv50_head_mode *m = &asyh->mode;
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u32 blankus;
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drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
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/*
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* DRM modes are defined in terms of a repeating interval
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* starting with the active display area. The hardware modes
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* are defined in terms of a repeating interval starting one
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* unit (pixel or line) into the sync pulse. So, add bias.
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*/
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m->h.active = mode->crtc_htotal;
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m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
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m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
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m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
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m->v.active = mode->crtc_vtotal;
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m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
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m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
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m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
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/*XXX: Safe underestimate, even "0" works */
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blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
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blankus *= 1000;
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blankus /= mode->crtc_clock;
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m->v.blankus = blankus;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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m->v.blank2e = m->v.active + m->v.blanke;
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m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
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m->v.active = (m->v.active * 2) + 1;
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m->interlace = true;
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} else {
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m->v.blank2e = 0;
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m->v.blank2s = 1;
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m->interlace = false;
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}
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m->clock = mode->crtc_clock;
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asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
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asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
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asyh->set.or = head->func->or != NULL;
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asyh->set.mode = true;
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}
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static int
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nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
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{
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struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
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crtc);
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struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
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crtc);
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struct nouveau_drm *drm = nouveau_drm(crtc->dev);
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struct nv50_head *head = nv50_head(crtc);
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struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state);
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struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
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struct nouveau_conn_atom *asyc = NULL;
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struct drm_connector_state *conns;
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struct drm_connector *conn;
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int i, ret;
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bool check_lut = asyh->state.color_mgmt_changed ||
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memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw));
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NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
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if (check_lut) {
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ret = nv50_head_atomic_check_lut(head, asyh);
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if (ret)
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return ret;
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}
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if (asyh->state.active) {
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for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
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if (conns->crtc == crtc) {
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asyc = nouveau_conn_atom(conns);
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break;
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}
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}
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if (armh->state.active) {
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if (asyc) {
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if (asyh->state.mode_changed)
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asyc->set.scaler = true;
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if (armh->base.depth != asyh->base.depth)
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asyc->set.dither = true;
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}
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} else {
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if (asyc)
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asyc->set.mask = ~0;
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asyh->set.mask = ~0;
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asyh->set.or = head->func->or != NULL;
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}
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if (asyh->state.mode_changed || asyh->state.connectors_changed)
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nv50_head_atomic_check_mode(head, asyh);
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if (check_lut)
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asyh->olut.visible = asyh->olut.handle != 0;
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if (asyc) {
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if (asyc->set.scaler)
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nv50_head_atomic_check_view(armh, asyh, asyc);
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if (asyc->set.dither)
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nv50_head_atomic_check_dither(armh, asyh, asyc);
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if (asyc->set.procamp)
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nv50_head_atomic_check_procamp(armh, asyh, asyc);
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}
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if (head->func->core_calc) {
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head->func->core_calc(head, asyh);
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if (!asyh->core.visible)
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asyh->olut.visible = false;
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}
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asyh->set.base = armh->base.cpp != asyh->base.cpp;
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asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
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} else {
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asyh->olut.visible = false;
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asyh->core.visible = false;
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asyh->curs.visible = false;
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asyh->base.cpp = 0;
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asyh->ovly.cpp = 0;
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}
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if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
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if (asyh->core.visible) {
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if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
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asyh->set.core = true;
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} else
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if (armh->core.visible) {
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asyh->clr.core = true;
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}
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if (asyh->curs.visible) {
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if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
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asyh->set.curs = true;
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} else
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if (armh->curs.visible) {
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asyh->clr.curs = true;
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}
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if (asyh->olut.visible) {
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if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
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asyh->set.olut = true;
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} else
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if (armh->olut.visible) {
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asyh->clr.olut = true;
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}
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} else {
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asyh->clr.olut = armh->olut.visible;
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asyh->clr.core = armh->core.visible;
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asyh->clr.curs = armh->curs.visible;
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asyh->set.olut = asyh->olut.visible;
|
|
asyh->set.core = asyh->core.visible;
|
|
asyh->set.curs = asyh->curs.visible;
|
|
}
|
|
|
|
ret = nv50_crc_atomic_check_head(head, asyh, armh);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (asyh->clr.mask || asyh->set.mask)
|
|
nv50_atom(asyh->state.state)->lock_core = true;
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs
|
|
nv50_head_help = {
|
|
.atomic_check = nv50_head_atomic_check,
|
|
.get_scanout_position = nouveau_display_scanoutpos,
|
|
};
|
|
|
|
static void
|
|
nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *state)
|
|
{
|
|
struct nv50_head_atom *asyh = nv50_head_atom(state);
|
|
__drm_atomic_helper_crtc_destroy_state(&asyh->state);
|
|
kfree(asyh);
|
|
}
|
|
|
|
static struct drm_crtc_state *
|
|
nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
|
|
{
|
|
struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
|
|
struct nv50_head_atom *asyh;
|
|
if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
|
|
return NULL;
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
|
|
asyh->wndw = armh->wndw;
|
|
asyh->view = armh->view;
|
|
asyh->mode = armh->mode;
|
|
asyh->olut = armh->olut;
|
|
asyh->core = armh->core;
|
|
asyh->curs = armh->curs;
|
|
asyh->base = armh->base;
|
|
asyh->ovly = armh->ovly;
|
|
asyh->dither = armh->dither;
|
|
asyh->procamp = armh->procamp;
|
|
asyh->crc = armh->crc;
|
|
asyh->or = armh->or;
|
|
asyh->dp = armh->dp;
|
|
asyh->clr.mask = 0;
|
|
asyh->set.mask = 0;
|
|
return &asyh->state;
|
|
}
|
|
|
|
static void
|
|
nv50_head_reset(struct drm_crtc *crtc)
|
|
{
|
|
struct nv50_head_atom *asyh;
|
|
|
|
if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
|
|
return;
|
|
|
|
if (crtc->state)
|
|
nv50_head_atomic_destroy_state(crtc, crtc->state);
|
|
|
|
__drm_atomic_helper_crtc_reset(crtc, &asyh->state);
|
|
}
|
|
|
|
static int
|
|
nv50_head_late_register(struct drm_crtc *crtc)
|
|
{
|
|
return nv50_head_crc_late_register(nv50_head(crtc));
|
|
}
|
|
|
|
static void
|
|
nv50_head_destroy(struct drm_crtc *crtc)
|
|
{
|
|
struct nv50_head *head = nv50_head(crtc);
|
|
|
|
nvif_event_dtor(&head->base.vblank);
|
|
nvif_head_dtor(&head->base.head);
|
|
nv50_lut_fini(&head->olut);
|
|
drm_crtc_cleanup(crtc);
|
|
kfree(head);
|
|
}
|
|
|
|
static const struct drm_crtc_funcs
|
|
nv50_head_func = {
|
|
.reset = nv50_head_reset,
|
|
.destroy = nv50_head_destroy,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
|
|
.atomic_destroy_state = nv50_head_atomic_destroy_state,
|
|
.enable_vblank = nouveau_display_vblank_enable,
|
|
.disable_vblank = nouveau_display_vblank_disable,
|
|
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
|
|
.late_register = nv50_head_late_register,
|
|
};
|
|
|
|
static const struct drm_crtc_funcs
|
|
nvd9_head_func = {
|
|
.reset = nv50_head_reset,
|
|
.destroy = nv50_head_destroy,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
|
|
.atomic_destroy_state = nv50_head_atomic_destroy_state,
|
|
.enable_vblank = nouveau_display_vblank_enable,
|
|
.disable_vblank = nouveau_display_vblank_disable,
|
|
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
|
|
.verify_crc_source = nv50_crc_verify_source,
|
|
.get_crc_sources = nv50_crc_get_sources,
|
|
.set_crc_source = nv50_crc_set_source,
|
|
.late_register = nv50_head_late_register,
|
|
};
|
|
|
|
static int
|
|
nv50_head_vblank_handler(struct nvif_event *event, void *repv, u32 repc)
|
|
{
|
|
struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank);
|
|
|
|
if (drm_crtc_handle_vblank(&nv_crtc->base))
|
|
nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
|
|
|
|
return NVIF_EVENT_KEEP;
|
|
}
|
|
|
|
struct nv50_head *
|
|
nv50_head_create(struct drm_device *dev, int index)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_drm(dev);
|
|
struct nv50_disp *disp = nv50_disp(dev);
|
|
struct nv50_head *head;
|
|
struct nv50_wndw *base, *ovly, *curs;
|
|
struct nouveau_crtc *nv_crtc;
|
|
struct drm_crtc *crtc;
|
|
const struct drm_crtc_funcs *funcs;
|
|
int ret;
|
|
|
|
head = kzalloc(sizeof(*head), GFP_KERNEL);
|
|
if (!head)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
head->func = disp->core->func->head;
|
|
head->base.index = index;
|
|
|
|
if (disp->disp->object.oclass < GF110_DISP)
|
|
funcs = &nv50_head_func;
|
|
else
|
|
funcs = &nvd9_head_func;
|
|
|
|
if (disp->disp->object.oclass < GV100_DISP) {
|
|
ret = nv50_base_new(drm, head->base.index, &base);
|
|
ret = nv50_ovly_new(drm, head->base.index, &ovly);
|
|
} else {
|
|
ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
|
|
head->base.index * 2 + 0, &base);
|
|
ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
|
|
head->base.index * 2 + 1, &ovly);
|
|
}
|
|
if (ret == 0)
|
|
ret = nv50_curs_new(drm, head->base.index, &curs);
|
|
if (ret) {
|
|
kfree(head);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
nv_crtc = &head->base;
|
|
crtc = &nv_crtc->base;
|
|
drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
|
|
funcs, "head-%d", head->base.index);
|
|
drm_crtc_helper_add(crtc, &nv50_head_help);
|
|
/* Keep the legacy gamma size at 256 to avoid compatibility issues */
|
|
drm_mode_crtc_set_gamma_size(crtc, 256);
|
|
drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
|
|
disp->disp->object.oclass >= GF110_DISP,
|
|
head->func->olut_size);
|
|
|
|
if (head->func->olut_set) {
|
|
ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
|
|
if (ret) {
|
|
nv50_head_destroy(crtc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
}
|
|
|
|
ret = nvif_head_ctor(disp->disp, head->base.base.name, head->base.index, &head->base.head);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
ret = nvif_head_vblank_event_ctor(&head->base.head, "kmsVbl", nv50_head_vblank_handler,
|
|
false, &nv_crtc->vblank);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
return head;
|
|
}
|