379 lines
9.0 KiB
C
379 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* for STMicroelectronics.
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*/
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#include <linux/moduleparam.h>
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#include <linux/seq_file.h>
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#include <drm/drm_print.h>
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#include "sti_compositor.h"
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#include "sti_mixer.h"
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#include "sti_vtg.h"
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/* Module parameter to set the background color of the mixer */
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static unsigned int bkg_color = 0x000000;
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MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
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module_param_named(bkgcolor, bkg_color, int, 0644);
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/* regs offset */
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#define GAM_MIXER_CTL 0x00
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#define GAM_MIXER_BKC 0x04
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#define GAM_MIXER_BCO 0x0C
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#define GAM_MIXER_BCS 0x10
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#define GAM_MIXER_AVO 0x28
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#define GAM_MIXER_AVS 0x2C
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#define GAM_MIXER_CRB 0x34
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#define GAM_MIXER_ACT 0x38
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#define GAM_MIXER_MBP 0x3C
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#define GAM_MIXER_MX0 0x80
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/* id for depth of CRB reg */
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#define GAM_DEPTH_VID0_ID 1
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#define GAM_DEPTH_VID1_ID 2
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#define GAM_DEPTH_GDP0_ID 3
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#define GAM_DEPTH_GDP1_ID 4
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#define GAM_DEPTH_GDP2_ID 5
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#define GAM_DEPTH_GDP3_ID 6
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#define GAM_DEPTH_MASK_ID 7
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/* mask in CTL reg */
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#define GAM_CTL_BACK_MASK BIT(0)
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#define GAM_CTL_VID0_MASK BIT(1)
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#define GAM_CTL_VID1_MASK BIT(2)
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#define GAM_CTL_GDP0_MASK BIT(3)
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#define GAM_CTL_GDP1_MASK BIT(4)
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#define GAM_CTL_GDP2_MASK BIT(5)
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#define GAM_CTL_GDP3_MASK BIT(6)
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#define GAM_CTL_CURSOR_MASK BIT(9)
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const char *sti_mixer_to_str(struct sti_mixer *mixer)
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{
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switch (mixer->id) {
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case STI_MIXER_MAIN:
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return "MAIN_MIXER";
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case STI_MIXER_AUX:
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return "AUX_MIXER";
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default:
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return "<UNKNOWN MIXER>";
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}
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}
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static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
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{
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return readl(mixer->regs + reg_id);
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}
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static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
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u32 reg_id, u32 val)
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{
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writel(val, mixer->regs + reg_id);
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}
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#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
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sti_mixer_reg_read(mixer, reg))
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static void mixer_dbg_ctl(struct seq_file *s, int val)
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{
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unsigned int i;
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int count = 0;
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char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0",
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"GDP1", "GDP2", "GDP3"};
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seq_puts(s, "\tEnabled: ");
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for (i = 0; i < 7; i++) {
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if (val & 1) {
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seq_printf(s, "%s ", disp_layer[i]);
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count++;
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}
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val = val >> 1;
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}
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val = val >> 2;
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if (val & 1) {
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seq_puts(s, "CURS ");
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count++;
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}
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if (!count)
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seq_puts(s, "Nothing");
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}
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static void mixer_dbg_crb(struct seq_file *s, int val)
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{
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int i;
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seq_puts(s, "\tDepth: ");
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for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
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switch (val & GAM_DEPTH_MASK_ID) {
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case GAM_DEPTH_VID0_ID:
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seq_puts(s, "VID0");
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break;
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case GAM_DEPTH_VID1_ID:
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seq_puts(s, "VID1");
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break;
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case GAM_DEPTH_GDP0_ID:
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seq_puts(s, "GDP0");
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break;
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case GAM_DEPTH_GDP1_ID:
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seq_puts(s, "GDP1");
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break;
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case GAM_DEPTH_GDP2_ID:
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seq_puts(s, "GDP2");
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break;
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case GAM_DEPTH_GDP3_ID:
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seq_puts(s, "GDP3");
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break;
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default:
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seq_puts(s, "---");
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}
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if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1)
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seq_puts(s, " < ");
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val = val >> 3;
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}
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}
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static void mixer_dbg_mxn(struct seq_file *s, void *addr)
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{
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int i;
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for (i = 1; i < 8; i++)
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seq_printf(s, "-0x%08X", (int)readl(addr + i * 4));
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}
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static int mixer_dbg_show(struct seq_file *s, void *arg)
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{
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struct drm_info_node *node = s->private;
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struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data;
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seq_printf(s, "%s: (vaddr = 0x%p)",
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sti_mixer_to_str(mixer), mixer->regs);
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DBGFS_DUMP(GAM_MIXER_CTL);
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mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL));
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DBGFS_DUMP(GAM_MIXER_BKC);
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DBGFS_DUMP(GAM_MIXER_BCO);
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DBGFS_DUMP(GAM_MIXER_BCS);
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DBGFS_DUMP(GAM_MIXER_AVO);
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DBGFS_DUMP(GAM_MIXER_AVS);
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DBGFS_DUMP(GAM_MIXER_CRB);
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mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
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DBGFS_DUMP(GAM_MIXER_ACT);
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DBGFS_DUMP(GAM_MIXER_MBP);
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DBGFS_DUMP(GAM_MIXER_MX0);
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mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0);
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seq_putc(s, '\n');
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return 0;
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}
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static struct drm_info_list mixer0_debugfs_files[] = {
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{ "mixer_main", mixer_dbg_show, 0, NULL },
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};
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static struct drm_info_list mixer1_debugfs_files[] = {
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{ "mixer_aux", mixer_dbg_show, 0, NULL },
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};
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void sti_mixer_debugfs_init(struct sti_mixer *mixer, struct drm_minor *minor)
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{
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unsigned int i;
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struct drm_info_list *mixer_debugfs_files;
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int nb_files;
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switch (mixer->id) {
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case STI_MIXER_MAIN:
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mixer_debugfs_files = mixer0_debugfs_files;
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nb_files = ARRAY_SIZE(mixer0_debugfs_files);
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break;
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case STI_MIXER_AUX:
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mixer_debugfs_files = mixer1_debugfs_files;
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nb_files = ARRAY_SIZE(mixer1_debugfs_files);
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break;
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default:
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return;
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}
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for (i = 0; i < nb_files; i++)
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mixer_debugfs_files[i].data = mixer;
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drm_debugfs_create_files(mixer_debugfs_files,
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nb_files,
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minor->debugfs_root, minor);
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}
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void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
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{
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u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
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val &= ~GAM_CTL_BACK_MASK;
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val |= enable;
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sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
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}
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static void sti_mixer_set_background_color(struct sti_mixer *mixer,
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unsigned int rgb)
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{
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sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
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}
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static void sti_mixer_set_background_area(struct sti_mixer *mixer,
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struct drm_display_mode *mode)
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{
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u32 ydo, xdo, yds, xds;
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ydo = sti_vtg_get_line_number(*mode, 0);
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yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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xdo = sti_vtg_get_pixel_number(*mode, 0);
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xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
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sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
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}
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int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane)
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{
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int plane_id, depth = plane->drm_plane.state->normalized_zpos;
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unsigned int i;
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u32 mask, val;
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switch (plane->desc) {
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case STI_GDP_0:
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plane_id = GAM_DEPTH_GDP0_ID;
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break;
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case STI_GDP_1:
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plane_id = GAM_DEPTH_GDP1_ID;
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break;
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case STI_GDP_2:
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plane_id = GAM_DEPTH_GDP2_ID;
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break;
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case STI_GDP_3:
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plane_id = GAM_DEPTH_GDP3_ID;
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break;
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case STI_HQVDP_0:
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plane_id = GAM_DEPTH_VID0_ID;
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break;
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case STI_CURSOR:
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/* no need to set depth for cursor */
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return 0;
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default:
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DRM_ERROR("Unknown plane %d\n", plane->desc);
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return 1;
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}
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/* Search if a previous depth was already assigned to the plane */
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val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
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for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
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mask = GAM_DEPTH_MASK_ID << (3 * i);
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if ((val & mask) == plane_id << (3 * i))
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break;
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}
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mask |= GAM_DEPTH_MASK_ID << (3 * depth);
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plane_id = plane_id << (3 * depth);
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DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
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sti_plane_to_str(plane), depth);
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dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
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plane_id, mask);
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val &= ~mask;
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val |= plane_id;
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sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
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dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
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sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
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return 0;
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}
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int sti_mixer_active_video_area(struct sti_mixer *mixer,
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struct drm_display_mode *mode)
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{
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u32 ydo, xdo, yds, xds;
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ydo = sti_vtg_get_line_number(*mode, 0);
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yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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xdo = sti_vtg_get_pixel_number(*mode, 0);
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xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
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sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
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sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
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sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
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sti_mixer_set_background_color(mixer, bkg_color);
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sti_mixer_set_background_area(mixer, mode);
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sti_mixer_set_background_status(mixer, true);
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return 0;
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}
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static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
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{
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switch (plane->desc) {
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case STI_BACK:
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return GAM_CTL_BACK_MASK;
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case STI_GDP_0:
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return GAM_CTL_GDP0_MASK;
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case STI_GDP_1:
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return GAM_CTL_GDP1_MASK;
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case STI_GDP_2:
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return GAM_CTL_GDP2_MASK;
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case STI_GDP_3:
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return GAM_CTL_GDP3_MASK;
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case STI_HQVDP_0:
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return GAM_CTL_VID0_MASK;
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case STI_CURSOR:
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return GAM_CTL_CURSOR_MASK;
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default:
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return 0;
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}
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}
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int sti_mixer_set_plane_status(struct sti_mixer *mixer,
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struct sti_plane *plane, bool status)
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{
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u32 mask, val;
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DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
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sti_mixer_to_str(mixer), sti_plane_to_str(plane));
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mask = sti_mixer_get_plane_mask(plane);
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if (!mask) {
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DRM_ERROR("Can't find layer mask\n");
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return -EINVAL;
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}
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val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
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val &= ~mask;
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val |= status ? mask : 0;
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sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
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return 0;
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}
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struct sti_mixer *sti_mixer_create(struct device *dev,
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struct drm_device *drm_dev,
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int id,
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void __iomem *baseaddr)
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{
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struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
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dev_dbg(dev, "%s\n", __func__);
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if (!mixer) {
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DRM_ERROR("Failed to allocated memory for mixer\n");
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return NULL;
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}
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mixer->regs = baseaddr;
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mixer->dev = dev;
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mixer->id = id;
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DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
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sti_mixer_to_str(mixer), mixer->regs);
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return mixer;
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}
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