482 lines
12 KiB
C
482 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2010-2011, 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014, Sony Mobile Communications Inc.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#define PON_REV2 0x01
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#define PON_SUBTYPE 0x05
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#define PON_SUBTYPE_PRIMARY 0x01
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#define PON_SUBTYPE_SECONDARY 0x02
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#define PON_SUBTYPE_1REG 0x03
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#define PON_SUBTYPE_GEN2_PRIMARY 0x04
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#define PON_SUBTYPE_GEN2_SECONDARY 0x05
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#define PON_SUBTYPE_GEN3_PBS 0x08
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#define PON_SUBTYPE_GEN3_HLOS 0x09
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#define PON_RT_STS 0x10
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#define PON_KPDPWR_N_SET BIT(0)
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#define PON_RESIN_N_SET BIT(1)
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#define PON_GEN3_RESIN_N_SET BIT(6)
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#define PON_GEN3_KPDPWR_N_SET BIT(7)
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#define PON_PS_HOLD_RST_CTL 0x5a
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#define PON_PS_HOLD_RST_CTL2 0x5b
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#define PON_PS_HOLD_ENABLE BIT(7)
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#define PON_PS_HOLD_TYPE_MASK 0x0f
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#define PON_PS_HOLD_TYPE_WARM_RESET 1
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#define PON_PS_HOLD_TYPE_SHUTDOWN 4
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#define PON_PS_HOLD_TYPE_HARD_RESET 7
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#define PON_PULL_CTL 0x70
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#define PON_KPDPWR_PULL_UP BIT(1)
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#define PON_RESIN_PULL_UP BIT(0)
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#define PON_DBC_CTL 0x71
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#define PON_DBC_DELAY_MASK_GEN1 0x7
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#define PON_DBC_DELAY_MASK_GEN2 0xf
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#define PON_DBC_SHIFT_GEN1 6
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#define PON_DBC_SHIFT_GEN2 14
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struct pm8941_data {
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unsigned int pull_up_bit;
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unsigned int status_bit;
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bool supports_ps_hold_poff_config;
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bool supports_debounce_config;
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bool has_pon_pbs;
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const char *name;
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const char *phys;
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};
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struct pm8941_pwrkey {
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struct device *dev;
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int irq;
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u32 baseaddr;
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u32 pon_pbs_baseaddr;
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struct regmap *regmap;
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struct input_dev *input;
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unsigned int revision;
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unsigned int subtype;
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struct notifier_block reboot_notifier;
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u32 code;
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u32 sw_debounce_time_us;
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ktime_t sw_debounce_end_time;
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bool last_status;
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const struct pm8941_data *data;
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};
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static int pm8941_reboot_notify(struct notifier_block *nb,
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unsigned long code, void *unused)
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{
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struct pm8941_pwrkey *pwrkey = container_of(nb, struct pm8941_pwrkey,
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reboot_notifier);
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unsigned int enable_reg;
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unsigned int reset_type;
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int error;
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/* PMICs with revision 0 have the enable bit in same register as ctrl */
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if (pwrkey->revision == 0)
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enable_reg = PON_PS_HOLD_RST_CTL;
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else
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enable_reg = PON_PS_HOLD_RST_CTL2;
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error = regmap_update_bits(pwrkey->regmap,
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pwrkey->baseaddr + enable_reg,
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PON_PS_HOLD_ENABLE,
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0);
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if (error)
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dev_err(pwrkey->dev,
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"unable to clear ps hold reset enable: %d\n",
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error);
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/*
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* Updates of PON_PS_HOLD_ENABLE requires 3 sleep cycles between
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* writes.
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*/
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usleep_range(100, 1000);
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switch (code) {
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case SYS_HALT:
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case SYS_POWER_OFF:
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reset_type = PON_PS_HOLD_TYPE_SHUTDOWN;
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break;
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case SYS_RESTART:
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default:
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if (reboot_mode == REBOOT_WARM)
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reset_type = PON_PS_HOLD_TYPE_WARM_RESET;
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else
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reset_type = PON_PS_HOLD_TYPE_HARD_RESET;
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break;
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}
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error = regmap_update_bits(pwrkey->regmap,
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pwrkey->baseaddr + PON_PS_HOLD_RST_CTL,
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PON_PS_HOLD_TYPE_MASK,
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reset_type);
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if (error)
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dev_err(pwrkey->dev, "unable to set ps hold reset type: %d\n",
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error);
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error = regmap_update_bits(pwrkey->regmap,
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pwrkey->baseaddr + enable_reg,
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PON_PS_HOLD_ENABLE,
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PON_PS_HOLD_ENABLE);
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if (error)
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dev_err(pwrkey->dev, "unable to re-set enable: %d\n", error);
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return NOTIFY_DONE;
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}
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static irqreturn_t pm8941_pwrkey_irq(int irq, void *_data)
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{
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struct pm8941_pwrkey *pwrkey = _data;
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unsigned int sts;
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int err;
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if (pwrkey->sw_debounce_time_us) {
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if (ktime_before(ktime_get(), pwrkey->sw_debounce_end_time)) {
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dev_dbg(pwrkey->dev,
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"ignoring key event received before debounce end %llu us\n",
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pwrkey->sw_debounce_end_time);
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return IRQ_HANDLED;
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}
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}
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err = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_RT_STS, &sts);
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if (err)
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return IRQ_HANDLED;
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sts &= pwrkey->data->status_bit;
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if (pwrkey->sw_debounce_time_us && !sts)
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pwrkey->sw_debounce_end_time = ktime_add_us(ktime_get(),
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pwrkey->sw_debounce_time_us);
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/*
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* Simulate a press event in case a release event occurred without a
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* corresponding press event.
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*/
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if (!pwrkey->last_status && !sts) {
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input_report_key(pwrkey->input, pwrkey->code, 1);
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input_sync(pwrkey->input);
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}
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pwrkey->last_status = sts;
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input_report_key(pwrkey->input, pwrkey->code, sts);
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input_sync(pwrkey->input);
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return IRQ_HANDLED;
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}
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static int pm8941_pwrkey_sw_debounce_init(struct pm8941_pwrkey *pwrkey)
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{
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unsigned int val, addr, mask;
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int error;
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if (pwrkey->data->has_pon_pbs && !pwrkey->pon_pbs_baseaddr) {
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dev_err(pwrkey->dev,
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"PON_PBS address missing, can't read HW debounce time\n");
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return 0;
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}
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if (pwrkey->pon_pbs_baseaddr)
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addr = pwrkey->pon_pbs_baseaddr + PON_DBC_CTL;
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else
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addr = pwrkey->baseaddr + PON_DBC_CTL;
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error = regmap_read(pwrkey->regmap, addr, &val);
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if (error)
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return error;
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if (pwrkey->subtype >= PON_SUBTYPE_GEN2_PRIMARY)
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mask = 0xf;
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else
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mask = 0x7;
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pwrkey->sw_debounce_time_us =
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2 * USEC_PER_SEC / (1 << (mask - (val & mask)));
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dev_dbg(pwrkey->dev, "SW debounce time = %u us\n",
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pwrkey->sw_debounce_time_us);
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return 0;
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}
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static int pm8941_pwrkey_suspend(struct device *dev)
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{
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struct pm8941_pwrkey *pwrkey = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(pwrkey->irq);
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return 0;
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}
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static int pm8941_pwrkey_resume(struct device *dev)
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{
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struct pm8941_pwrkey *pwrkey = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(pwrkey->irq);
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(pm8941_pwr_key_pm_ops,
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pm8941_pwrkey_suspend, pm8941_pwrkey_resume);
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static int pm8941_pwrkey_probe(struct platform_device *pdev)
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{
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struct pm8941_pwrkey *pwrkey;
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bool pull_up;
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struct device *parent;
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struct device_node *regmap_node;
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const __be32 *addr;
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u32 req_delay, mask, delay_shift;
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int error;
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if (of_property_read_u32(pdev->dev.of_node, "debounce", &req_delay))
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req_delay = 15625;
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if (req_delay > 2000000 || req_delay == 0) {
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dev_err(&pdev->dev, "invalid debounce time: %u\n", req_delay);
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return -EINVAL;
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}
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pull_up = of_property_read_bool(pdev->dev.of_node, "bias-pull-up");
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pwrkey = devm_kzalloc(&pdev->dev, sizeof(*pwrkey), GFP_KERNEL);
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if (!pwrkey)
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return -ENOMEM;
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pwrkey->dev = &pdev->dev;
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pwrkey->data = of_device_get_match_data(&pdev->dev);
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parent = pdev->dev.parent;
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regmap_node = pdev->dev.of_node;
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pwrkey->regmap = dev_get_regmap(parent, NULL);
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if (!pwrkey->regmap) {
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regmap_node = parent->of_node;
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/*
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* We failed to get regmap for parent. Let's see if we are
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* a child of pon node and read regmap and reg from its
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* parent.
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*/
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pwrkey->regmap = dev_get_regmap(parent->parent, NULL);
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if (!pwrkey->regmap) {
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dev_err(&pdev->dev, "failed to locate regmap\n");
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return -ENODEV;
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}
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}
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addr = of_get_address(regmap_node, 0, NULL, NULL);
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if (!addr) {
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dev_err(&pdev->dev, "reg property missing\n");
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return -EINVAL;
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}
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pwrkey->baseaddr = be32_to_cpup(addr);
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if (pwrkey->data->has_pon_pbs) {
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/* PON_PBS base address is optional */
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addr = of_get_address(regmap_node, 1, NULL, NULL);
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if (addr)
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pwrkey->pon_pbs_baseaddr = be32_to_cpup(addr);
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}
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pwrkey->irq = platform_get_irq(pdev, 0);
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if (pwrkey->irq < 0)
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return pwrkey->irq;
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error = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_REV2,
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&pwrkey->revision);
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if (error) {
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dev_err(&pdev->dev, "failed to read revision: %d\n", error);
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return error;
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}
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error = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_SUBTYPE,
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&pwrkey->subtype);
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if (error) {
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dev_err(&pdev->dev, "failed to read subtype: %d\n", error);
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return error;
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}
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error = of_property_read_u32(pdev->dev.of_node, "linux,code",
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&pwrkey->code);
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if (error) {
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dev_dbg(&pdev->dev,
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"no linux,code assuming power (%d)\n", error);
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pwrkey->code = KEY_POWER;
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}
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pwrkey->input = devm_input_allocate_device(&pdev->dev);
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if (!pwrkey->input) {
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dev_dbg(&pdev->dev, "unable to allocate input device\n");
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return -ENOMEM;
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}
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input_set_capability(pwrkey->input, EV_KEY, pwrkey->code);
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pwrkey->input->name = pwrkey->data->name;
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pwrkey->input->phys = pwrkey->data->phys;
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if (pwrkey->data->supports_debounce_config) {
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if (pwrkey->subtype >= PON_SUBTYPE_GEN2_PRIMARY) {
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mask = PON_DBC_DELAY_MASK_GEN2;
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delay_shift = PON_DBC_SHIFT_GEN2;
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} else {
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mask = PON_DBC_DELAY_MASK_GEN1;
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delay_shift = PON_DBC_SHIFT_GEN1;
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}
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req_delay = (req_delay << delay_shift) / USEC_PER_SEC;
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req_delay = ilog2(req_delay);
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error = regmap_update_bits(pwrkey->regmap,
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pwrkey->baseaddr + PON_DBC_CTL,
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mask,
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req_delay);
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if (error) {
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dev_err(&pdev->dev, "failed to set debounce: %d\n",
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error);
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return error;
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}
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}
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error = pm8941_pwrkey_sw_debounce_init(pwrkey);
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if (error)
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return error;
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if (pwrkey->data->pull_up_bit) {
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error = regmap_update_bits(pwrkey->regmap,
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pwrkey->baseaddr + PON_PULL_CTL,
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pwrkey->data->pull_up_bit,
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pull_up ? pwrkey->data->pull_up_bit :
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0);
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if (error) {
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dev_err(&pdev->dev, "failed to set pull: %d\n", error);
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return error;
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}
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}
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error = devm_request_threaded_irq(&pdev->dev, pwrkey->irq,
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NULL, pm8941_pwrkey_irq,
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IRQF_ONESHOT,
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pwrkey->data->name, pwrkey);
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if (error) {
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dev_err(&pdev->dev, "failed requesting IRQ: %d\n", error);
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return error;
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}
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error = input_register_device(pwrkey->input);
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if (error) {
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dev_err(&pdev->dev, "failed to register input device: %d\n",
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error);
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return error;
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}
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if (pwrkey->data->supports_ps_hold_poff_config) {
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pwrkey->reboot_notifier.notifier_call = pm8941_reboot_notify;
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error = register_reboot_notifier(&pwrkey->reboot_notifier);
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if (error) {
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dev_err(&pdev->dev, "failed to register reboot notifier: %d\n",
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error);
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return error;
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}
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}
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platform_set_drvdata(pdev, pwrkey);
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device_init_wakeup(&pdev->dev, 1);
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return 0;
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}
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static int pm8941_pwrkey_remove(struct platform_device *pdev)
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{
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struct pm8941_pwrkey *pwrkey = platform_get_drvdata(pdev);
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if (pwrkey->data->supports_ps_hold_poff_config)
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unregister_reboot_notifier(&pwrkey->reboot_notifier);
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return 0;
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}
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static const struct pm8941_data pwrkey_data = {
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.pull_up_bit = PON_KPDPWR_PULL_UP,
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.status_bit = PON_KPDPWR_N_SET,
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.name = "pm8941_pwrkey",
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.phys = "pm8941_pwrkey/input0",
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.supports_ps_hold_poff_config = true,
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.supports_debounce_config = true,
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.has_pon_pbs = false,
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};
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static const struct pm8941_data resin_data = {
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.pull_up_bit = PON_RESIN_PULL_UP,
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.status_bit = PON_RESIN_N_SET,
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.name = "pm8941_resin",
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.phys = "pm8941_resin/input0",
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.supports_ps_hold_poff_config = true,
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.supports_debounce_config = true,
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.has_pon_pbs = false,
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};
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static const struct pm8941_data pon_gen3_pwrkey_data = {
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.status_bit = PON_GEN3_KPDPWR_N_SET,
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.name = "pmic_pwrkey",
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.phys = "pmic_pwrkey/input0",
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.supports_ps_hold_poff_config = false,
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.supports_debounce_config = false,
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.has_pon_pbs = true,
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};
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static const struct pm8941_data pon_gen3_resin_data = {
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.status_bit = PON_GEN3_RESIN_N_SET,
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.name = "pmic_resin",
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.phys = "pmic_resin/input0",
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.supports_ps_hold_poff_config = false,
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.supports_debounce_config = false,
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.has_pon_pbs = true,
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};
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static const struct of_device_id pm8941_pwr_key_id_table[] = {
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{ .compatible = "qcom,pm8941-pwrkey", .data = &pwrkey_data },
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{ .compatible = "qcom,pm8941-resin", .data = &resin_data },
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{ .compatible = "qcom,pmk8350-pwrkey", .data = &pon_gen3_pwrkey_data },
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{ .compatible = "qcom,pmk8350-resin", .data = &pon_gen3_resin_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pm8941_pwr_key_id_table);
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static struct platform_driver pm8941_pwrkey_driver = {
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.probe = pm8941_pwrkey_probe,
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.remove = pm8941_pwrkey_remove,
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.driver = {
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.name = "pm8941-pwrkey",
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.pm = pm_sleep_ptr(&pm8941_pwr_key_pm_ops),
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.of_match_table = of_match_ptr(pm8941_pwr_key_id_table),
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},
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};
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module_platform_driver(pm8941_pwrkey_driver);
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MODULE_DESCRIPTION("PM8941 Power Key driver");
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MODULE_LICENSE("GPL v2");
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