448 lines
12 KiB
C
448 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <media/drv-intf/saa7146_vv.h>
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static int vbi_pixel_to_capture = 720 * 2;
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static int vbi_workaround(struct saa7146_dev *dev)
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{
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struct saa7146_vv *vv = dev->vv_data;
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u32 *cpu;
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dma_addr_t dma_addr;
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int count = 0;
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int i;
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DECLARE_WAITQUEUE(wait, current);
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DEB_VBI("dev:%p\n", dev);
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/* once again, a bug in the saa7146: the brs acquisition
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is buggy and especially the BXO-counter does not work
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as specified. there is this workaround, but please
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don't let me explain it. ;-) */
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cpu = dma_alloc_coherent(&dev->pci->dev, 4096, &dma_addr, GFP_KERNEL);
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if (NULL == cpu)
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return -ENOMEM;
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/* setup some basic programming, just for the workaround */
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saa7146_write(dev, BASE_EVEN3, dma_addr);
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saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture);
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saa7146_write(dev, PROT_ADDR3, dma_addr+4096);
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saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
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saa7146_write(dev, BASE_PAGE3, 0x0);
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saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
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saa7146_write(dev, MC2, MASK_04|MASK_20);
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* BXO = 1h, BRS to outbound */
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WRITE_RPS1(0xc000008c);
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/* wait for vbi_a or vbi_b*/
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if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
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DEB_D("...using port b\n");
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B);
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B);
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/*
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WRITE_RPS1(CMD_PAUSE | MASK_09);
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*/
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} else {
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DEB_D("...using port a\n");
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WRITE_RPS1(CMD_PAUSE | MASK_10);
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}
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/* upload brs */
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WRITE_RPS1(CMD_UPLOAD | MASK_08);
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
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WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
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/* wait for brs_done */
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WRITE_RPS1(CMD_PAUSE | MASK_08);
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/* upload brs */
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WRITE_RPS1(CMD_UPLOAD | MASK_08);
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/* load video-dma3 NumLines3 and NumBytes3 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
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/* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
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WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
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WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
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/* wait for brs_done */
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WRITE_RPS1(CMD_PAUSE | MASK_08);
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/* upload brs and video-dma3*/
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WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
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/* load mc2 register: enable dma3 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
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WRITE_RPS1(MASK_20 | MASK_04);
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/* generate interrupt */
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WRITE_RPS1(CMD_INTERRUPT);
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/* stop rps1 */
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WRITE_RPS1(CMD_STOP);
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/* we have to do the workaround twice to be sure that
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everything is ok */
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for(i = 0; i < 2; i++) {
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/* indicate to the irq handler that we do the workaround */
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saa7146_write(dev, MC2, MASK_31|MASK_15);
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saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
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saa7146_write(dev, MC2, MASK_04|MASK_20);
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/* enable rps1 irqs */
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SAA7146_IER_ENABLE(dev,MASK_28);
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/* prepare to wait to be woken up by the irq-handler */
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add_wait_queue(&vv->vbi_wq, &wait);
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set_current_state(TASK_INTERRUPTIBLE);
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/* start rps1 to enable workaround */
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saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
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saa7146_write(dev, MC1, (MASK_13 | MASK_29));
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schedule();
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DEB_VBI("brs bug workaround %d/1\n", i);
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remove_wait_queue(&vv->vbi_wq, &wait);
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__set_current_state(TASK_RUNNING);
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/* disable rps1 irqs */
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SAA7146_IER_DISABLE(dev,MASK_28);
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/* stop video-dma3 */
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saa7146_write(dev, MC1, MASK_20);
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if(signal_pending(current)) {
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DEB_VBI("aborted (rps:0x%08x)\n",
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saa7146_read(dev, RPS_ADDR1));
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/* stop rps1 for sure */
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saa7146_write(dev, MC1, MASK_29);
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dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
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return -EINTR;
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}
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}
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dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
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return 0;
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}
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static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
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{
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struct saa7146_vv *vv = dev->vv_data;
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struct saa7146_video_dma vdma3;
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int count = 0;
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unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
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unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
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/*
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vdma3.base_even = 0xc8000000+2560*70;
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vdma3.base_odd = 0xc8000000;
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vdma3.prot_addr = 0xc8000000+2560*164;
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vdma3.pitch = 2560;
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vdma3.base_page = 0;
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vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
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*/
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vdma3.base_even = buf->pt[2].offset;
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vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture;
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vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
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vdma3.pitch = vbi_pixel_to_capture;
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vdma3.base_page = buf->pt[2].dma | ME1;
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vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
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saa7146_write_out_dma(dev, 3, &vdma3);
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/* write beginning of rps-program */
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count = 0;
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/* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
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/* we don't wait here for the first field anymore. this is different from the video
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capture and might cause that the first buffer is only half filled (with only
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one field). but since this is some sort of streaming data, this is not that negative.
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but by doing this, we can use the whole engine from videobuf-dma-sg.c... */
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/*
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
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*/
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/* set bit 1 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
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WRITE_RPS1(MASK_28 | MASK_12);
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/* turn on video-dma3 */
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WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
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WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
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WRITE_RPS1(MASK_04 | MASK_20); /* => values */
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/* wait for o_fid_a/b / e_fid_a/b toggle */
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WRITE_RPS1(CMD_PAUSE | o_wait);
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WRITE_RPS1(CMD_PAUSE | e_wait);
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/* generate interrupt */
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WRITE_RPS1(CMD_INTERRUPT);
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/* stop */
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WRITE_RPS1(CMD_STOP);
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/* enable rps1 irqs */
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SAA7146_IER_ENABLE(dev, MASK_28);
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/* write the address of the rps-program */
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saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
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/* turn on rps */
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saa7146_write(dev, MC1, (MASK_13 | MASK_29));
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}
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static int buffer_activate(struct saa7146_dev *dev,
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struct saa7146_buf *buf,
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struct saa7146_buf *next)
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{
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struct saa7146_vv *vv = dev->vv_data;
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DEB_VBI("dev:%p, buf:%p, next:%p\n", dev, buf, next);
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saa7146_set_vbi_capture(dev,buf,next);
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mod_timer(&vv->vbi_dmaq.timeout, jiffies+BUFFER_TIMEOUT);
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return 0;
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}
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/* ------------------------------------------------------------------ */
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static int queue_setup(struct vb2_queue *q,
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unsigned int *num_buffers, unsigned int *num_planes,
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unsigned int sizes[], struct device *alloc_devs[])
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{
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unsigned int size = 16 * 2 * vbi_pixel_to_capture;
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if (*num_planes)
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return sizes[0] < size ? -EINVAL : 0;
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*num_planes = 1;
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sizes[0] = size;
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return 0;
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}
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static void buf_queue(struct vb2_buffer *vb)
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{
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struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
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struct vb2_queue *vq = vb->vb2_queue;
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struct saa7146_dev *dev = vb2_get_drv_priv(vq);
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struct saa7146_buf *buf = container_of(vbuf, struct saa7146_buf, vb);
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unsigned long flags;
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spin_lock_irqsave(&dev->slock, flags);
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saa7146_buffer_queue(dev, &dev->vv_data->vbi_dmaq, buf);
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spin_unlock_irqrestore(&dev->slock, flags);
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}
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static int buf_init(struct vb2_buffer *vb)
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{
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struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
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struct saa7146_buf *buf = container_of(vbuf, struct saa7146_buf, vb);
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struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
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struct scatterlist *list = sgt->sgl;
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int length = sgt->nents;
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struct vb2_queue *vq = vb->vb2_queue;
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struct saa7146_dev *dev = vb2_get_drv_priv(vq);
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int ret;
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buf->activate = buffer_activate;
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saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
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ret = saa7146_pgtable_build_single(dev->pci, &buf->pt[2],
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list, length);
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if (ret)
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saa7146_pgtable_free(dev->pci, &buf->pt[2]);
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return ret;
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}
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static int buf_prepare(struct vb2_buffer *vb)
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{
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unsigned int size = 16 * 2 * vbi_pixel_to_capture;
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if (vb2_plane_size(vb, 0) < size)
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return -EINVAL;
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vb2_set_plane_payload(vb, 0, size);
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return 0;
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}
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static void buf_cleanup(struct vb2_buffer *vb)
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{
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struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
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struct saa7146_buf *buf = container_of(vbuf, struct saa7146_buf, vb);
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struct vb2_queue *vq = vb->vb2_queue;
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struct saa7146_dev *dev = vb2_get_drv_priv(vq);
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saa7146_pgtable_free(dev->pci, &buf->pt[2]);
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}
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static void return_buffers(struct vb2_queue *q, int state)
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{
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struct saa7146_dev *dev = vb2_get_drv_priv(q);
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struct saa7146_dmaqueue *dq = &dev->vv_data->vbi_dmaq;
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struct saa7146_buf *buf;
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if (dq->curr) {
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buf = dq->curr;
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dq->curr = NULL;
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vb2_buffer_done(&buf->vb.vb2_buf, state);
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}
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while (!list_empty(&dq->queue)) {
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buf = list_entry(dq->queue.next, struct saa7146_buf, list);
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list_del(&buf->list);
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vb2_buffer_done(&buf->vb.vb2_buf, state);
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}
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}
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static void vbi_stop(struct saa7146_dev *dev)
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{
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struct saa7146_vv *vv = dev->vv_data;
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unsigned long flags;
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DEB_VBI("dev:%p\n", dev);
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spin_lock_irqsave(&dev->slock,flags);
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/* disable rps1 */
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saa7146_write(dev, MC1, MASK_29);
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/* disable rps1 irqs */
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SAA7146_IER_DISABLE(dev, MASK_28);
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/* shut down dma 3 transfers */
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saa7146_write(dev, MC1, MASK_20);
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del_timer(&vv->vbi_dmaq.timeout);
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del_timer(&vv->vbi_read_timeout);
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spin_unlock_irqrestore(&dev->slock, flags);
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}
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static void vbi_read_timeout(struct timer_list *t)
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{
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struct saa7146_vv *vv = from_timer(vv, t, vbi_read_timeout);
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struct saa7146_dev *dev = vv->vbi_dmaq.dev;
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DEB_VBI("dev:%p\n", dev);
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vbi_stop(dev);
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}
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static int vbi_begin(struct saa7146_dev *dev)
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{
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struct saa7146_vv *vv = dev->vv_data;
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u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
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int ret = 0;
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DEB_VBI("dev:%p\n", dev);
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ret = saa7146_res_get(dev, RESOURCE_DMA3_BRS);
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if (0 == ret) {
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DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
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return -EBUSY;
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}
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/* adjust arbitrition control for video dma 3 */
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arbtr_ctrl &= ~0x1f0000;
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arbtr_ctrl |= 0x1d0000;
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saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
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saa7146_write(dev, MC2, (MASK_04|MASK_20));
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vv->vbi_read_timeout.function = vbi_read_timeout;
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/* initialize the brs */
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if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
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saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
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} else {
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saa7146_write(dev, BRS_CTRL, 0x00000001);
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if (0 != (ret = vbi_workaround(dev))) {
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DEB_VBI("vbi workaround failed!\n");
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/* return ret;*/
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}
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}
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/* upload brs register */
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saa7146_write(dev, MC2, (MASK_08|MASK_24));
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return 0;
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}
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static int start_streaming(struct vb2_queue *q, unsigned int count)
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{
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struct saa7146_dev *dev = vb2_get_drv_priv(q);
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int ret;
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if (!vb2_is_streaming(&dev->vv_data->vbi_dmaq.q))
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dev->vv_data->seqnr = 0;
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ret = vbi_begin(dev);
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if (ret)
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return_buffers(q, VB2_BUF_STATE_QUEUED);
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return ret;
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}
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static void stop_streaming(struct vb2_queue *q)
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{
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struct saa7146_dev *dev = vb2_get_drv_priv(q);
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vbi_stop(dev);
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return_buffers(q, VB2_BUF_STATE_ERROR);
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saa7146_res_free(dev, RESOURCE_DMA3_BRS);
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}
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const struct vb2_ops vbi_qops = {
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.queue_setup = queue_setup,
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.buf_queue = buf_queue,
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.buf_init = buf_init,
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.buf_prepare = buf_prepare,
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.buf_cleanup = buf_cleanup,
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.start_streaming = start_streaming,
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.stop_streaming = stop_streaming,
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.wait_prepare = vb2_ops_wait_prepare,
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.wait_finish = vb2_ops_wait_finish,
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};
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/* ------------------------------------------------------------------ */
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static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv)
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{
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DEB_VBI("dev:%p\n", dev);
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INIT_LIST_HEAD(&vv->vbi_dmaq.queue);
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timer_setup(&vv->vbi_dmaq.timeout, saa7146_buffer_timeout, 0);
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vv->vbi_dmaq.dev = dev;
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init_waitqueue_head(&vv->vbi_wq);
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}
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static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status)
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{
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struct saa7146_vv *vv = dev->vv_data;
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spin_lock(&dev->slock);
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if (vv->vbi_dmaq.curr) {
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DEB_VBI("dev:%p, curr:%p\n", dev, vv->vbi_dmaq.curr);
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saa7146_buffer_finish(dev, &vv->vbi_dmaq, VB2_BUF_STATE_DONE);
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} else {
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DEB_VBI("dev:%p\n", dev);
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}
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saa7146_buffer_next(dev, &vv->vbi_dmaq, 1);
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spin_unlock(&dev->slock);
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}
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const struct saa7146_use_ops saa7146_vbi_uops = {
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.init = vbi_init,
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.irq_done = vbi_irq_done,
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};
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