657 lines
20 KiB
C
657 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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cx24110 - Single Chip Satellite Channel Receiver driver module
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Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
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work
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Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
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*/
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <media/dvb_frontend.h>
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#include "cx24110.h"
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struct cx24110_state {
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struct i2c_adapter* i2c;
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const struct cx24110_config* config;
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struct dvb_frontend frontend;
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u32 lastber;
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u32 lastbler;
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u32 lastesn0;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) printk(KERN_DEBUG "cx24110: " args); \
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} while (0)
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static struct {u8 reg; u8 data;} cx24110_regdata[]=
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/* Comments beginning with @ denote this value should
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be the default */
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{{0x09,0x01}, /* SoftResetAll */
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{0x09,0x00}, /* release reset */
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{0x01,0xe8}, /* MSB of code rate 27.5MS/s */
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{0x02,0x17}, /* middle byte " */
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{0x03,0x29}, /* LSB " */
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{0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
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{0x06,0xa5}, /* @ PLL 60MHz */
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{0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
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{0x0a,0x00}, /* @ partial chip disables, do not set */
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{0x0b,0x01}, /* set output clock in gapped mode, start signal low
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active for first byte */
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{0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
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{0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
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{0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
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to avoid starting the BER counter. Reset the
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CRC test bit. Finite counting selected */
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{0x15,0xff}, /* @ size of the limited time window for RS BER
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estimation. It is <value>*256 RS blocks, this
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gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
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{0x16,0x00}, /* @ enable all RS output ports */
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{0x17,0x04}, /* @ time window allowed for the RS to sync */
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{0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
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for automatically */
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/* leave the current code rate and normalization
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registers as they are after reset... */
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{0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
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only once */
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{0x23,0x18}, /* @ size of the limited time window for Viterbi BER
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estimation. It is <value>*65536 channel bits, i.e.
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approx. 38ms at 27.5MS/s, rate 3/4 */
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{0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
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/* leave front-end AGC parameters at default values */
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/* leave decimation AGC parameters at default values */
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{0x35,0x40}, /* disable all interrupts. They are not connected anyway */
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{0x36,0xff}, /* clear all interrupt pending flags */
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{0x37,0x00}, /* @ fully enable AutoAcqq state machine */
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{0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
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/* leave the equalizer parameters on their default values */
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/* leave the final AGC parameters on their default values */
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{0x41,0x00}, /* @ MSB of front-end derotator frequency */
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{0x42,0x00}, /* @ middle bytes " */
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{0x43,0x00}, /* @ LSB " */
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/* leave the carrier tracking loop parameters on default */
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/* leave the bit timing loop parameters at default */
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{0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
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/* the cx24108 data sheet for symbol rates above 15MS/s */
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{0x57,0x00}, /* @ Filter sigma delta enabled, positive */
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{0x61,0x95}, /* GPIO pins 1-4 have special function */
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{0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
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{0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
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{0x64,0x20}, /* GPIO 6 is input, all others are outputs */
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{0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
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{0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
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{0x73,0x00}, /* @ disable several demod bypasses */
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{0x74,0x00}, /* @ " */
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{0x75,0x00} /* @ " */
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/* the remaining registers are for SEC */
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};
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static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
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{
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u8 buf [] = { reg, data };
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struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
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int err;
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if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
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dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n",
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__func__, err, reg, data);
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return -EREMOTEIO;
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}
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return 0;
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}
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static int cx24110_readreg (struct cx24110_state* state, u8 reg)
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{
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int ret;
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u8 b0 [] = { reg };
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u8 b1 [] = { 0 };
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struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
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{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) return ret;
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return b1[0];
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}
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static int cx24110_set_inversion(struct cx24110_state *state,
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enum fe_spectral_inversion inversion)
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{
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/* fixme (low): error handling */
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switch (inversion) {
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case INVERSION_OFF:
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cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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/* AcqSpectrInvDis on. No idea why someone should want this */
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cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
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/* Initial value 0 at start of acq */
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cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
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/* current value 0 */
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/* The cx24110 manual tells us this reg is read-only.
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But what the heck... set it ayways */
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break;
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case INVERSION_ON:
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cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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/* AcqSpectrInvDis on. No idea why someone should want this */
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cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
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/* Initial value 1 at start of acq */
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cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
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/* current value 1 */
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break;
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case INVERSION_AUTO:
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cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
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/* AcqSpectrInvDis off. Leave initial & current states as is */
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int cx24110_set_fec(struct cx24110_state *state, enum fe_code_rate fec)
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{
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static const int rate[FEC_AUTO] = {-1, 1, 2, 3, 5, 7, -1};
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static const int g1[FEC_AUTO] = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1};
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static const int g2[FEC_AUTO] = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1};
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/* Well, the AutoAcq engine of the cx24106 and 24110 automatically
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searches all enabled viterbi rates, and can handle non-standard
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rates as well. */
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if (fec > FEC_AUTO)
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fec = FEC_AUTO;
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if (fec == FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
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cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf);
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/* clear AcqVitDis bit */
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cx24110_writereg(state, 0x18, 0xae);
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/* allow all DVB standard code rates */
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cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3);
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/* set nominal Viterbi rate 3/4 */
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cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3);
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/* set current Viterbi rate 3/4 */
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cx24110_writereg(state, 0x1a, 0x05);
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cx24110_writereg(state, 0x1b, 0x06);
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/* set the puncture registers for code rate 3/4 */
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return 0;
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} else {
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cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20);
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/* set AcqVitDis bit */
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if (rate[fec] < 0)
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return -EINVAL;
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cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]);
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/* set nominal Viterbi rate */
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cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]);
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/* set current Viterbi rate */
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cx24110_writereg(state, 0x1a, g1[fec]);
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cx24110_writereg(state, 0x1b, g2[fec]);
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/* not sure if this is the right way: I always used AutoAcq mode */
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}
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return 0;
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}
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static enum fe_code_rate cx24110_get_fec(struct cx24110_state *state)
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{
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int i;
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i=cx24110_readreg(state,0x22)&0x0f;
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if(!(i&0x08)) {
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return FEC_1_2 + i - 1;
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} else {
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/* fixme (low): a special code rate has been selected. In theory, we need to
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return a denominator value, a numerator value, and a pair of puncture
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maps to correctly describe this mode. But this should never happen in
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practice, because it cannot be set by cx24110_get_fec. */
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return FEC_NONE;
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}
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}
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static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
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{
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/* fixme (low): add error handling */
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u32 ratio;
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u32 tmp, fclk, BDRI;
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static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
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int i;
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dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
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if (srate>90999000UL/2)
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srate=90999000UL/2;
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if (srate<500000)
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srate=500000;
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for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
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;
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/* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
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and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
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R06[3:0] PLLphaseDetGain */
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tmp=cx24110_readreg(state,0x07)&0xfc;
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if(srate<90999000UL/4) { /* sample rate 45MHz*/
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cx24110_writereg(state,0x07,tmp);
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cx24110_writereg(state,0x06,0x78);
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fclk=90999000UL/2;
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} else if(srate<60666000UL/2) { /* sample rate 60MHz */
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cx24110_writereg(state,0x07,tmp|0x1);
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cx24110_writereg(state,0x06,0xa5);
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fclk=60666000UL;
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} else if(srate<80888000UL/2) { /* sample rate 80MHz */
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cx24110_writereg(state,0x07,tmp|0x2);
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cx24110_writereg(state,0x06,0x87);
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fclk=80888000UL;
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} else { /* sample rate 90MHz */
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cx24110_writereg(state,0x07,tmp|0x3);
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cx24110_writereg(state,0x06,0x78);
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fclk=90999000UL;
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}
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dprintk("cx24110 debug: fclk %d Hz\n",fclk);
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/* we need to divide two integers with approx. 27 bits in 32 bit
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arithmetic giving a 25 bit result */
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/* the maximum dividend is 90999000/2, 0x02b6446c, this number is
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also the most complex divisor. Hence, the dividend has,
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assuming 32bit unsigned arithmetic, 6 clear bits on top, the
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divisor 2 unused bits at the bottom. Also, the quotient is
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always less than 1/2. Borrowed from VES1893.c, of course */
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tmp=srate<<6;
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BDRI=fclk>>2;
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ratio=(tmp/BDRI);
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tmp=(tmp%BDRI)<<8;
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ratio=(ratio<<8)+(tmp/BDRI);
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tmp=(tmp%BDRI)<<8;
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ratio=(ratio<<8)+(tmp/BDRI);
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tmp=(tmp%BDRI)<<1;
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ratio=(ratio<<1)+(tmp/BDRI);
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dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
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dprintk("fclk = %d\n", fclk);
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dprintk("ratio= %08x\n", ratio);
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cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
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cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
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cx24110_writereg(state, 0x3, (ratio)&0xff);
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return 0;
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}
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static int _cx24110_pll_write (struct dvb_frontend* fe, const u8 buf[], int len)
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{
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struct cx24110_state *state = fe->demodulator_priv;
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if (len != 3)
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return -EINVAL;
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/* tuner data is 21 bits long, must be left-aligned in data */
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/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
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/* FIXME (low): add error handling, avoid infinite loops if HW fails... */
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cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
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cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
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/* if the auto tuner writer is still busy, clear it out */
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while (cx24110_readreg(state,0x6d)&0x80)
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cx24110_writereg(state,0x72,0);
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/* write the topmost 8 bits */
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cx24110_writereg(state,0x72,buf[0]);
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/* wait for the send to be completed */
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while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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;
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/* send another 8 bytes */
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cx24110_writereg(state,0x72,buf[1]);
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while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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;
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/* and the topmost 5 bits of this byte */
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cx24110_writereg(state,0x72,buf[2]);
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while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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;
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/* now strobe the enable line once */
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cx24110_writereg(state,0x6d,0x32);
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cx24110_writereg(state,0x6d,0x30);
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return 0;
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}
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static int cx24110_initfe(struct dvb_frontend* fe)
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{
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struct cx24110_state *state = fe->demodulator_priv;
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/* fixme (low): error handling */
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int i;
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dprintk("%s: init chip\n", __func__);
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for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
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cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
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}
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return 0;
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}
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static int cx24110_set_voltage(struct dvb_frontend *fe,
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enum fe_sec_voltage voltage)
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{
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struct cx24110_state *state = fe->demodulator_priv;
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switch (voltage) {
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case SEC_VOLTAGE_13:
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return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
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case SEC_VOLTAGE_18:
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return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
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default:
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return -EINVAL;
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}
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}
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static int cx24110_diseqc_send_burst(struct dvb_frontend *fe,
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enum fe_sec_mini_cmd burst)
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{
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int rv, bit;
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struct cx24110_state *state = fe->demodulator_priv;
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unsigned long timeout;
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if (burst == SEC_MINI_A)
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bit = 0x00;
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else if (burst == SEC_MINI_B)
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bit = 0x08;
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else
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return -EINVAL;
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rv = cx24110_readreg(state, 0x77);
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if (!(rv & 0x04))
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cx24110_writereg(state, 0x77, rv | 0x04);
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rv = cx24110_readreg(state, 0x76);
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cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
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timeout = jiffies + msecs_to_jiffies(100);
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while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
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; /* wait for LNB ready */
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return 0;
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}
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static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
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struct dvb_diseqc_master_cmd *cmd)
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{
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int i, rv;
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struct cx24110_state *state = fe->demodulator_priv;
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unsigned long timeout;
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if (cmd->msg_len < 3 || cmd->msg_len > 6)
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return -EINVAL; /* not implemented */
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for (i = 0; i < cmd->msg_len; i++)
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cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
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rv = cx24110_readreg(state, 0x77);
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if (rv & 0x04) {
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cx24110_writereg(state, 0x77, rv & ~0x04);
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msleep(30); /* reportedly fixes switching problems */
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}
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rv = cx24110_readreg(state, 0x76);
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cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
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timeout = jiffies + msecs_to_jiffies(100);
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while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
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; /* wait for LNB ready */
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return 0;
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}
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static int cx24110_read_status(struct dvb_frontend *fe,
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enum fe_status *status)
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{
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struct cx24110_state *state = fe->demodulator_priv;
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int sync = cx24110_readreg (state, 0x55);
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*status = 0;
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if (sync & 0x10)
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*status |= FE_HAS_SIGNAL;
|
|
|
|
if (sync & 0x08)
|
|
*status |= FE_HAS_CARRIER;
|
|
|
|
sync = cx24110_readreg (state, 0x08);
|
|
|
|
if (sync & 0x40)
|
|
*status |= FE_HAS_VITERBI;
|
|
|
|
if (sync & 0x20)
|
|
*status |= FE_HAS_SYNC;
|
|
|
|
if ((sync & 0x60) == 0x60)
|
|
*status |= FE_HAS_LOCK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
|
/* fixme (maybe): value range is 16 bit. Scale? */
|
|
if(cx24110_readreg(state,0x24)&0x10) {
|
|
/* the Viterbi error counter has finished one counting window */
|
|
cx24110_writereg(state,0x24,0x04); /* select the ber reg */
|
|
state->lastber=cx24110_readreg(state,0x25)|
|
|
(cx24110_readreg(state,0x26)<<8);
|
|
cx24110_writereg(state,0x24,0x04); /* start new count window */
|
|
cx24110_writereg(state,0x24,0x14);
|
|
}
|
|
*ber = state->lastber;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
|
/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
|
|
u8 signal = cx24110_readreg (state, 0x27)+128;
|
|
*signal_strength = (signal << 8) | signal;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
|
/* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
|
|
if(cx24110_readreg(state,0x6a)&0x80) {
|
|
/* the Es/N0 error counter has finished one counting window */
|
|
state->lastesn0=cx24110_readreg(state,0x69)|
|
|
(cx24110_readreg(state,0x68)<<8);
|
|
cx24110_writereg(state,0x6a,0x84); /* start new count window */
|
|
}
|
|
*snr = state->lastesn0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
|
if(cx24110_readreg(state,0x10)&0x40) {
|
|
/* the RS error counter has finished one counting window */
|
|
cx24110_writereg(state,0x10,0x60); /* select the byer reg */
|
|
(void)(cx24110_readreg(state, 0x12) |
|
|
(cx24110_readreg(state, 0x13) << 8) |
|
|
(cx24110_readreg(state, 0x14) << 16));
|
|
cx24110_writereg(state,0x10,0x70); /* select the bler reg */
|
|
state->lastbler=cx24110_readreg(state,0x12)|
|
|
(cx24110_readreg(state,0x13)<<8)|
|
|
(cx24110_readreg(state,0x14)<<16);
|
|
cx24110_writereg(state,0x10,0x20); /* start new count window */
|
|
}
|
|
*ucblocks = state->lastbler;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
|
|
|
if (fe->ops.tuner_ops.set_params) {
|
|
fe->ops.tuner_ops.set_params(fe);
|
|
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
|
|
}
|
|
|
|
cx24110_set_inversion(state, p->inversion);
|
|
cx24110_set_fec(state, p->fec_inner);
|
|
cx24110_set_symbolrate(state, p->symbol_rate);
|
|
cx24110_writereg(state,0x04,0x05); /* start acquisition */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_get_frontend(struct dvb_frontend *fe,
|
|
struct dtv_frontend_properties *p)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
s32 afc; unsigned sclk;
|
|
|
|
/* cannot read back tuner settings (freq). Need to have some private storage */
|
|
|
|
sclk = cx24110_readreg (state, 0x07) & 0x03;
|
|
/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
|
|
* Need 64 bit arithmetic. Is thiss possible in the kernel? */
|
|
if (sclk==0) sclk=90999000L/2L;
|
|
else if (sclk==1) sclk=60666000L;
|
|
else if (sclk==2) sclk=80888000L;
|
|
else sclk=90999000L;
|
|
sclk>>=8;
|
|
afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
|
|
((sclk*cx24110_readreg (state, 0x45))>>8)+
|
|
((sclk*cx24110_readreg (state, 0x46))>>16);
|
|
|
|
p->frequency += afc;
|
|
p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
|
|
INVERSION_ON : INVERSION_OFF;
|
|
p->fec_inner = cx24110_get_fec(state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cx24110_set_tone(struct dvb_frontend *fe,
|
|
enum fe_sec_tone_mode tone)
|
|
{
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
|
return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
|
|
}
|
|
|
|
static void cx24110_release(struct dvb_frontend* fe)
|
|
{
|
|
struct cx24110_state* state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops cx24110_ops;
|
|
|
|
struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
|
|
struct i2c_adapter* i2c)
|
|
{
|
|
struct cx24110_state* state = NULL;
|
|
int ret;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
|
|
if (state == NULL) goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
state->lastber = 0;
|
|
state->lastbler = 0;
|
|
state->lastesn0 = 0;
|
|
|
|
/* check if the demod is there */
|
|
ret = cx24110_readreg(state, 0x00);
|
|
if ((ret != 0x5a) && (ret != 0x69)) goto error;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static const struct dvb_frontend_ops cx24110_ops = {
|
|
.delsys = { SYS_DVBS },
|
|
.info = {
|
|
.name = "Conexant CX24110 DVB-S",
|
|
.frequency_min_hz = 950 * MHz,
|
|
.frequency_max_hz = 2150 * MHz,
|
|
.frequency_stepsize_hz = 1011 * kHz,
|
|
.frequency_tolerance_hz = 29500 * kHz,
|
|
.symbol_rate_min = 1000000,
|
|
.symbol_rate_max = 45000000,
|
|
.caps = FE_CAN_INVERSION_AUTO |
|
|
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
|
FE_CAN_QPSK | FE_CAN_RECOVER
|
|
},
|
|
|
|
.release = cx24110_release,
|
|
|
|
.init = cx24110_initfe,
|
|
.write = _cx24110_pll_write,
|
|
.set_frontend = cx24110_set_frontend,
|
|
.get_frontend = cx24110_get_frontend,
|
|
.read_status = cx24110_read_status,
|
|
.read_ber = cx24110_read_ber,
|
|
.read_signal_strength = cx24110_read_signal_strength,
|
|
.read_snr = cx24110_read_snr,
|
|
.read_ucblocks = cx24110_read_ucblocks,
|
|
|
|
.diseqc_send_master_cmd = cx24110_send_diseqc_msg,
|
|
.set_tone = cx24110_set_tone,
|
|
.set_voltage = cx24110_set_voltage,
|
|
.diseqc_send_burst = cx24110_diseqc_send_burst,
|
|
};
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
|
|
|
MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
|
|
MODULE_AUTHOR("Peter Hettkamp");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL_GPL(cx24110_attach);
|