1059 lines
28 KiB
C
1059 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip AXI PCIe host controller driver
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*
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* Copyright (c) 2016 Rockchip, Inc.
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*
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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* Wenrui Li <wenrui.li@rock-chips.com>
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*
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* Bits taken from Synopsys DesignWare Host controller driver and
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* ARM PCI Host generic driver.
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*/
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#include <linux/bitrev.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/regmap.h>
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#include "../pci.h"
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#include "pcie-rockchip.h"
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static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
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{
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u32 status;
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
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status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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}
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static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
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{
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u32 status;
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
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status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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}
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static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
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{
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u32 val;
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/* Update Tx credit maximum update interval */
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val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
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val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
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val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
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rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
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}
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static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
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struct pci_bus *bus, int dev)
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{
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/*
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* Access only one slot on each root port.
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* Do not read more than one device on the bus directly attached
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* to RC's downstream side.
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*/
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if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent))
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return dev == 0;
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return 1;
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}
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static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
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{
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u32 val;
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u8 map;
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if (rockchip->legacy_phy)
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return GENMASK(MAX_LANE_NUM - 1, 0);
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val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
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map = val & PCIE_CORE_LANE_MAP_MASK;
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/* The link may be using a reverse-indexed mapping. */
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if (val & PCIE_CORE_LANE_MAP_REVERSE)
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map = bitrev8(map) >> 4;
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return map;
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}
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static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
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if (!IS_ALIGNED((uintptr_t)addr, size)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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if (size == 4) {
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*val = readl(addr);
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} else if (size == 2) {
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*val = readw(addr);
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} else if (size == 1) {
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*val = readb(addr);
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} else {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
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int where, int size, u32 val)
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{
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u32 mask, tmp, offset;
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void __iomem *addr;
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offset = where & ~0x3;
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addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
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if (size == 4) {
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writel(val, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
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/*
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* N.B. This read/modify/write isn't safe in general because it can
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* corrupt RW1C bits in adjacent registers. But the hardware
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* doesn't support smaller writes.
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*/
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tmp = readl(addr) & mask;
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tmp |= val << ((where & 0x3) * 8);
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writel(tmp, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
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struct pci_bus *bus, u32 devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
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if (!IS_ALIGNED((uintptr_t)addr, size)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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if (pci_is_root_bus(bus->parent))
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rockchip_pcie_cfg_configuration_accesses(rockchip,
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AXI_WRAPPER_TYPE0_CFG);
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else
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rockchip_pcie_cfg_configuration_accesses(rockchip,
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AXI_WRAPPER_TYPE1_CFG);
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if (size == 4) {
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*val = readl(addr);
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} else if (size == 2) {
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*val = readw(addr);
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} else if (size == 1) {
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*val = readb(addr);
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} else {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
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struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
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if (!IS_ALIGNED((uintptr_t)addr, size))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (pci_is_root_bus(bus->parent))
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rockchip_pcie_cfg_configuration_accesses(rockchip,
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AXI_WRAPPER_TYPE0_CFG);
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else
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rockchip_pcie_cfg_configuration_accesses(rockchip,
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AXI_WRAPPER_TYPE1_CFG);
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr);
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else if (size == 1)
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writeb(val, addr);
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct rockchip_pcie *rockchip = bus->sysdata;
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if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (pci_is_root_bus(bus))
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return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
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return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
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val);
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}
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static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct rockchip_pcie *rockchip = bus->sysdata;
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if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (pci_is_root_bus(bus))
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return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
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return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
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val);
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}
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static struct pci_ops rockchip_pcie_ops = {
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.read = rockchip_pcie_rd_conf,
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.write = rockchip_pcie_wr_conf,
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};
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static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
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{
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int curr;
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u32 status, scale, power;
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if (IS_ERR(rockchip->vpcie3v3))
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return;
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/*
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* Set RC's captured slot power limit and scale if
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* vpcie3v3 available. The default values are both zero
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* which means the software should set these two according
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* to the actual power supply.
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*/
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curr = regulator_get_current_limit(rockchip->vpcie3v3);
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if (curr <= 0)
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return;
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scale = 3; /* 0.001x */
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curr = curr / 1000; /* convert to mA */
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power = (curr * 3300) / 1000; /* milliwatt */
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while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
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if (!scale) {
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dev_warn(rockchip->dev, "invalid power supply\n");
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return;
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}
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scale--;
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power = power / 10;
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}
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
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status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
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(scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
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}
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/**
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* rockchip_pcie_host_init_port - Initialize hardware
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* @rockchip: PCIe port information
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*/
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static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->dev;
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int err, i = MAX_LANE_NUM;
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u32 status;
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gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
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err = rockchip_pcie_init_port(rockchip);
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if (err)
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return err;
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/* Fix the transmitted FTS count desired to exit from L0s. */
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status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
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status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
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(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
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rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
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rockchip_pcie_set_power_limit(rockchip);
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/* Set RC's clock architecture as common clock */
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
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status |= PCI_EXP_LNKSTA_SLC << 16;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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/* Set RC's RCB to 128 */
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
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status |= PCI_EXP_LNKCTL_RCB;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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/* Enable Gen1 training */
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rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
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PCIE_CLIENT_CONFIG);
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gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
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/* 500ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
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status, PCIE_LINK_UP(status), 20,
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500 * USEC_PER_MSEC);
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if (err) {
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dev_err(dev, "PCIe link training gen1 timeout!\n");
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goto err_power_off_phy;
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}
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if (rockchip->link_gen == 2) {
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/*
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* Enable retrain for gen2. This should be configured only after
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* gen1 finished.
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*/
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
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status |= PCI_EXP_LNKCTL_RL;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
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status, PCIE_LINK_IS_GEN2(status), 20,
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500 * USEC_PER_MSEC);
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if (err)
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dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
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}
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/* Check the final link width from negotiated lane counter from MGMT */
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status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
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status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
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PCIE_CORE_PL_CONF_LANE_SHIFT);
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dev_dbg(dev, "current link width is x%d\n", status);
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/* Power off unused lane(s) */
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rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
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for (i = 0; i < MAX_LANE_NUM; i++) {
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if (!(rockchip->lanes_map & BIT(i))) {
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dev_dbg(dev, "idling lane %d\n", i);
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phy_power_off(rockchip->phys[i]);
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}
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}
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rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
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PCIE_CORE_CONFIG_VENDOR);
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rockchip_pcie_write(rockchip,
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PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
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PCIE_RC_CONFIG_RID_CCR);
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/* Clear THP cap's next cap pointer to remove L1 substate cap */
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
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status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
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/* Clear L0s from RC's link cap */
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if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
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status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
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}
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
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status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK;
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status |= PCIE_RC_CONFIG_DCSR_MPS_256;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
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return 0;
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err_power_off_phy:
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while (i--)
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phy_power_off(rockchip->phys[i]);
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i = MAX_LANE_NUM;
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while (i--)
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phy_exit(rockchip->phys[i]);
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return err;
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}
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static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
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{
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struct rockchip_pcie *rockchip = arg;
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struct device *dev = rockchip->dev;
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u32 reg;
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u32 sub_reg;
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reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
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if (reg & PCIE_CLIENT_INT_LOCAL) {
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dev_dbg(dev, "local interrupt received\n");
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sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
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if (sub_reg & PCIE_CORE_INT_PRFPE)
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dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
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if (sub_reg & PCIE_CORE_INT_CRFPE)
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dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
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if (sub_reg & PCIE_CORE_INT_RRPE)
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dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
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if (sub_reg & PCIE_CORE_INT_PRFO)
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dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
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if (sub_reg & PCIE_CORE_INT_CRFO)
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dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
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if (sub_reg & PCIE_CORE_INT_RT)
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dev_dbg(dev, "replay timer timed out\n");
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if (sub_reg & PCIE_CORE_INT_RTR)
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dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
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if (sub_reg & PCIE_CORE_INT_PE)
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dev_dbg(dev, "phy error detected on receive side\n");
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if (sub_reg & PCIE_CORE_INT_MTR)
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dev_dbg(dev, "malformed TLP received from the link\n");
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if (sub_reg & PCIE_CORE_INT_UCR)
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dev_dbg(dev, "malformed TLP received from the link\n");
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if (sub_reg & PCIE_CORE_INT_FCE)
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dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
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if (sub_reg & PCIE_CORE_INT_CT)
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dev_dbg(dev, "a request timed out waiting for completion\n");
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if (sub_reg & PCIE_CORE_INT_UTC)
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dev_dbg(dev, "unmapped TC error\n");
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if (sub_reg & PCIE_CORE_INT_MMVC)
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dev_dbg(dev, "MSI mask register changes\n");
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rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
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} else if (reg & PCIE_CLIENT_INT_PHY) {
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dev_dbg(dev, "phy link changes\n");
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rockchip_pcie_update_txcredit_mui(rockchip);
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rockchip_pcie_clr_bw_int(rockchip);
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}
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rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
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PCIE_CLIENT_INT_STATUS);
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return IRQ_HANDLED;
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}
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static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
|
|
{
|
|
struct rockchip_pcie *rockchip = arg;
|
|
struct device *dev = rockchip->dev;
|
|
u32 reg;
|
|
|
|
reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
|
|
if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
|
|
dev_dbg(dev, "legacy done interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_MSG)
|
|
dev_dbg(dev, "message done interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_HOT_RST)
|
|
dev_dbg(dev, "hot reset interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_DPA)
|
|
dev_dbg(dev, "dpa interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_FATAL_ERR)
|
|
dev_dbg(dev, "fatal error interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
|
|
dev_dbg(dev, "no fatal error interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_CORR_ERR)
|
|
dev_dbg(dev, "correctable error interrupt received\n");
|
|
|
|
if (reg & PCIE_CLIENT_INT_PHY)
|
|
dev_dbg(dev, "phy interrupt received\n");
|
|
|
|
rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
|
|
PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
|
|
PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
|
|
PCIE_CLIENT_INT_NFATAL_ERR |
|
|
PCIE_CLIENT_INT_CORR_ERR |
|
|
PCIE_CLIENT_INT_PHY),
|
|
PCIE_CLIENT_INT_STATUS);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
|
|
struct device *dev = rockchip->dev;
|
|
u32 reg;
|
|
u32 hwirq;
|
|
int ret;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
|
|
reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
|
|
|
|
while (reg) {
|
|
hwirq = ffs(reg) - 1;
|
|
reg &= ~BIT(hwirq);
|
|
|
|
ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq);
|
|
if (ret)
|
|
dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
|
|
{
|
|
int irq, err;
|
|
struct device *dev = rockchip->dev;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
irq = platform_get_irq_byname(pdev, "sys");
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
|
|
IRQF_SHARED, "pcie-sys", rockchip);
|
|
if (err) {
|
|
dev_err(dev, "failed to request PCIe subsystem IRQ\n");
|
|
return err;
|
|
}
|
|
|
|
irq = platform_get_irq_byname(pdev, "legacy");
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
irq_set_chained_handler_and_data(irq,
|
|
rockchip_pcie_legacy_int_handler,
|
|
rockchip);
|
|
|
|
irq = platform_get_irq_byname(pdev, "client");
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
|
|
IRQF_SHARED, "pcie-client", rockchip);
|
|
if (err) {
|
|
dev_err(dev, "failed to request PCIe client IRQ\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* rockchip_pcie_parse_host_dt - Parse Device Tree
|
|
* @rockchip: PCIe port information
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
|
|
{
|
|
struct device *dev = rockchip->dev;
|
|
int err;
|
|
|
|
err = rockchip_pcie_parse_dt(rockchip);
|
|
if (err)
|
|
return err;
|
|
|
|
rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
|
|
if (IS_ERR(rockchip->vpcie12v)) {
|
|
if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
|
|
return PTR_ERR(rockchip->vpcie12v);
|
|
dev_info(dev, "no vpcie12v regulator found\n");
|
|
}
|
|
|
|
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
|
|
if (IS_ERR(rockchip->vpcie3v3)) {
|
|
if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
|
|
return PTR_ERR(rockchip->vpcie3v3);
|
|
dev_info(dev, "no vpcie3v3 regulator found\n");
|
|
}
|
|
|
|
rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
|
|
if (IS_ERR(rockchip->vpcie1v8))
|
|
return PTR_ERR(rockchip->vpcie1v8);
|
|
|
|
rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
|
|
if (IS_ERR(rockchip->vpcie0v9))
|
|
return PTR_ERR(rockchip->vpcie0v9);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
|
|
{
|
|
struct device *dev = rockchip->dev;
|
|
int err;
|
|
|
|
if (!IS_ERR(rockchip->vpcie12v)) {
|
|
err = regulator_enable(rockchip->vpcie12v);
|
|
if (err) {
|
|
dev_err(dev, "fail to enable vpcie12v regulator\n");
|
|
goto err_out;
|
|
}
|
|
}
|
|
|
|
if (!IS_ERR(rockchip->vpcie3v3)) {
|
|
err = regulator_enable(rockchip->vpcie3v3);
|
|
if (err) {
|
|
dev_err(dev, "fail to enable vpcie3v3 regulator\n");
|
|
goto err_disable_12v;
|
|
}
|
|
}
|
|
|
|
err = regulator_enable(rockchip->vpcie1v8);
|
|
if (err) {
|
|
dev_err(dev, "fail to enable vpcie1v8 regulator\n");
|
|
goto err_disable_3v3;
|
|
}
|
|
|
|
err = regulator_enable(rockchip->vpcie0v9);
|
|
if (err) {
|
|
dev_err(dev, "fail to enable vpcie0v9 regulator\n");
|
|
goto err_disable_1v8;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_disable_1v8:
|
|
regulator_disable(rockchip->vpcie1v8);
|
|
err_disable_3v3:
|
|
if (!IS_ERR(rockchip->vpcie3v3))
|
|
regulator_disable(rockchip->vpcie3v3);
|
|
err_disable_12v:
|
|
if (!IS_ERR(rockchip->vpcie12v))
|
|
regulator_disable(rockchip->vpcie12v);
|
|
err_out:
|
|
return err;
|
|
}
|
|
|
|
static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
|
|
{
|
|
rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
|
|
(~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
|
|
rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
|
|
PCIE_CORE_INT_MASK);
|
|
|
|
rockchip_pcie_enable_bw_int(rockchip);
|
|
}
|
|
|
|
static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
|
irq_set_chip_data(irq, domain->host_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops intx_domain_ops = {
|
|
.map = rockchip_pcie_intx_map,
|
|
};
|
|
|
|
static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
|
|
{
|
|
struct device *dev = rockchip->dev;
|
|
struct device_node *intc = of_get_next_child(dev->of_node, NULL);
|
|
|
|
if (!intc) {
|
|
dev_err(dev, "missing child interrupt-controller node\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
|
|
&intx_domain_ops, rockchip);
|
|
of_node_put(intc);
|
|
if (!rockchip->irq_domain) {
|
|
dev_err(dev, "failed to get a INTx IRQ domain\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
|
|
int region_no, int type, u8 num_pass_bits,
|
|
u32 lower_addr, u32 upper_addr)
|
|
{
|
|
u32 ob_addr_0;
|
|
u32 ob_addr_1;
|
|
u32 ob_desc_0;
|
|
u32 aw_offset;
|
|
|
|
if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
|
|
return -EINVAL;
|
|
if (num_pass_bits + 1 < 8)
|
|
return -EINVAL;
|
|
if (num_pass_bits > 63)
|
|
return -EINVAL;
|
|
if (region_no == 0) {
|
|
if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
|
|
return -EINVAL;
|
|
}
|
|
if (region_no != 0) {
|
|
if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
|
|
return -EINVAL;
|
|
}
|
|
|
|
aw_offset = (region_no << OB_REG_SIZE_SHIFT);
|
|
|
|
ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
|
|
ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
|
|
ob_addr_1 = upper_addr;
|
|
ob_desc_0 = (1 << 23 | type);
|
|
|
|
rockchip_pcie_write(rockchip, ob_addr_0,
|
|
PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
|
|
rockchip_pcie_write(rockchip, ob_addr_1,
|
|
PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
|
|
rockchip_pcie_write(rockchip, ob_desc_0,
|
|
PCIE_CORE_OB_REGION_DESC0 + aw_offset);
|
|
rockchip_pcie_write(rockchip, 0,
|
|
PCIE_CORE_OB_REGION_DESC1 + aw_offset);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
|
|
int region_no, u8 num_pass_bits,
|
|
u32 lower_addr, u32 upper_addr)
|
|
{
|
|
u32 ib_addr_0;
|
|
u32 ib_addr_1;
|
|
u32 aw_offset;
|
|
|
|
if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
|
|
return -EINVAL;
|
|
if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
|
|
return -EINVAL;
|
|
if (num_pass_bits > 63)
|
|
return -EINVAL;
|
|
|
|
aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
|
|
|
|
ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
|
|
ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
|
|
ib_addr_1 = upper_addr;
|
|
|
|
rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
|
|
rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
|
|
{
|
|
struct device *dev = rockchip->dev;
|
|
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
|
|
struct resource_entry *entry;
|
|
u64 pci_addr, size;
|
|
int offset;
|
|
int err;
|
|
int reg_no;
|
|
|
|
rockchip_pcie_cfg_configuration_accesses(rockchip,
|
|
AXI_WRAPPER_TYPE0_CFG);
|
|
entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
|
|
if (!entry)
|
|
return -ENODEV;
|
|
|
|
size = resource_size(entry->res);
|
|
pci_addr = entry->res->start - entry->offset;
|
|
rockchip->msg_bus_addr = pci_addr;
|
|
|
|
for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
|
|
err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
|
|
AXI_WRAPPER_MEM_WRITE,
|
|
20 - 1,
|
|
pci_addr + (reg_no << 20),
|
|
0);
|
|
if (err) {
|
|
dev_err(dev, "program RC mem outbound ATU failed\n");
|
|
return err;
|
|
}
|
|
}
|
|
|
|
err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
|
|
if (err) {
|
|
dev_err(dev, "program RC mem inbound ATU failed\n");
|
|
return err;
|
|
}
|
|
|
|
entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
|
|
if (!entry)
|
|
return -ENODEV;
|
|
|
|
/* store the register number offset to program RC io outbound ATU */
|
|
offset = size >> 20;
|
|
|
|
size = resource_size(entry->res);
|
|
pci_addr = entry->res->start - entry->offset;
|
|
|
|
for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
|
|
err = rockchip_pcie_prog_ob_atu(rockchip,
|
|
reg_no + 1 + offset,
|
|
AXI_WRAPPER_IO_WRITE,
|
|
20 - 1,
|
|
pci_addr + (reg_no << 20),
|
|
0);
|
|
if (err) {
|
|
dev_err(dev, "program RC io outbound ATU failed\n");
|
|
return err;
|
|
}
|
|
}
|
|
|
|
/* assign message regions */
|
|
rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
|
|
AXI_WRAPPER_NOR_MSG,
|
|
20 - 1, 0, 0);
|
|
|
|
rockchip->msg_bus_addr += ((reg_no + offset) << 20);
|
|
return err;
|
|
}
|
|
|
|
static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
|
|
{
|
|
u32 value;
|
|
int err;
|
|
|
|
/* send PME_TURN_OFF message */
|
|
writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
|
|
|
|
/* read LTSSM and wait for falling into L2 link state */
|
|
err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
|
|
value, PCIE_LINK_IS_L2(value), 20,
|
|
jiffies_to_usecs(5 * HZ));
|
|
if (err) {
|
|
dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_pcie_suspend_noirq(struct device *dev)
|
|
{
|
|
struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
/* disable core and cli int since we don't need to ack PME_ACK */
|
|
rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
|
|
PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
|
|
rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
|
|
|
|
ret = rockchip_pcie_wait_l2(rockchip);
|
|
if (ret) {
|
|
rockchip_pcie_enable_interrupts(rockchip);
|
|
return ret;
|
|
}
|
|
|
|
rockchip_pcie_deinit_phys(rockchip);
|
|
|
|
rockchip_pcie_disable_clocks(rockchip);
|
|
|
|
regulator_disable(rockchip->vpcie0v9);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_pcie_resume_noirq(struct device *dev)
|
|
{
|
|
struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
|
|
int err;
|
|
|
|
err = regulator_enable(rockchip->vpcie0v9);
|
|
if (err) {
|
|
dev_err(dev, "fail to enable vpcie0v9 regulator\n");
|
|
return err;
|
|
}
|
|
|
|
err = rockchip_pcie_enable_clocks(rockchip);
|
|
if (err)
|
|
goto err_disable_0v9;
|
|
|
|
err = rockchip_pcie_host_init_port(rockchip);
|
|
if (err)
|
|
goto err_pcie_resume;
|
|
|
|
err = rockchip_pcie_cfg_atu(rockchip);
|
|
if (err)
|
|
goto err_err_deinit_port;
|
|
|
|
/* Need this to enter L1 again */
|
|
rockchip_pcie_update_txcredit_mui(rockchip);
|
|
rockchip_pcie_enable_interrupts(rockchip);
|
|
|
|
return 0;
|
|
|
|
err_err_deinit_port:
|
|
rockchip_pcie_deinit_phys(rockchip);
|
|
err_pcie_resume:
|
|
rockchip_pcie_disable_clocks(rockchip);
|
|
err_disable_0v9:
|
|
regulator_disable(rockchip->vpcie0v9);
|
|
return err;
|
|
}
|
|
|
|
static int rockchip_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct rockchip_pcie *rockchip;
|
|
struct device *dev = &pdev->dev;
|
|
struct pci_host_bridge *bridge;
|
|
int err;
|
|
|
|
if (!dev->of_node)
|
|
return -ENODEV;
|
|
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
rockchip = pci_host_bridge_priv(bridge);
|
|
|
|
platform_set_drvdata(pdev, rockchip);
|
|
rockchip->dev = dev;
|
|
rockchip->is_rc = true;
|
|
|
|
err = rockchip_pcie_parse_host_dt(rockchip);
|
|
if (err)
|
|
return err;
|
|
|
|
err = rockchip_pcie_enable_clocks(rockchip);
|
|
if (err)
|
|
return err;
|
|
|
|
err = rockchip_pcie_set_vpcie(rockchip);
|
|
if (err) {
|
|
dev_err(dev, "failed to set vpcie regulator\n");
|
|
goto err_set_vpcie;
|
|
}
|
|
|
|
err = rockchip_pcie_host_init_port(rockchip);
|
|
if (err)
|
|
goto err_vpcie;
|
|
|
|
err = rockchip_pcie_init_irq_domain(rockchip);
|
|
if (err < 0)
|
|
goto err_deinit_port;
|
|
|
|
err = rockchip_pcie_cfg_atu(rockchip);
|
|
if (err)
|
|
goto err_remove_irq_domain;
|
|
|
|
rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
|
|
if (!rockchip->msg_region) {
|
|
err = -ENOMEM;
|
|
goto err_remove_irq_domain;
|
|
}
|
|
|
|
bridge->sysdata = rockchip;
|
|
bridge->ops = &rockchip_pcie_ops;
|
|
|
|
err = rockchip_pcie_setup_irq(rockchip);
|
|
if (err)
|
|
goto err_remove_irq_domain;
|
|
|
|
rockchip_pcie_enable_interrupts(rockchip);
|
|
|
|
err = pci_host_probe(bridge);
|
|
if (err < 0)
|
|
goto err_remove_irq_domain;
|
|
|
|
return 0;
|
|
|
|
err_remove_irq_domain:
|
|
irq_domain_remove(rockchip->irq_domain);
|
|
err_deinit_port:
|
|
rockchip_pcie_deinit_phys(rockchip);
|
|
err_vpcie:
|
|
if (!IS_ERR(rockchip->vpcie12v))
|
|
regulator_disable(rockchip->vpcie12v);
|
|
if (!IS_ERR(rockchip->vpcie3v3))
|
|
regulator_disable(rockchip->vpcie3v3);
|
|
regulator_disable(rockchip->vpcie1v8);
|
|
regulator_disable(rockchip->vpcie0v9);
|
|
err_set_vpcie:
|
|
rockchip_pcie_disable_clocks(rockchip);
|
|
return err;
|
|
}
|
|
|
|
static void rockchip_pcie_remove(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
|
|
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
|
|
|
|
pci_stop_root_bus(bridge->bus);
|
|
pci_remove_root_bus(bridge->bus);
|
|
irq_domain_remove(rockchip->irq_domain);
|
|
|
|
rockchip_pcie_deinit_phys(rockchip);
|
|
|
|
rockchip_pcie_disable_clocks(rockchip);
|
|
|
|
if (!IS_ERR(rockchip->vpcie12v))
|
|
regulator_disable(rockchip->vpcie12v);
|
|
if (!IS_ERR(rockchip->vpcie3v3))
|
|
regulator_disable(rockchip->vpcie3v3);
|
|
regulator_disable(rockchip->vpcie1v8);
|
|
regulator_disable(rockchip->vpcie0v9);
|
|
}
|
|
|
|
static const struct dev_pm_ops rockchip_pcie_pm_ops = {
|
|
NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
|
|
rockchip_pcie_resume_noirq)
|
|
};
|
|
|
|
static const struct of_device_id rockchip_pcie_of_match[] = {
|
|
{ .compatible = "rockchip,rk3399-pcie", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match);
|
|
|
|
static struct platform_driver rockchip_pcie_driver = {
|
|
.driver = {
|
|
.name = "rockchip-pcie",
|
|
.of_match_table = rockchip_pcie_of_match,
|
|
.pm = &rockchip_pcie_pm_ops,
|
|
},
|
|
.probe = rockchip_pcie_probe,
|
|
.remove_new = rockchip_pcie_remove,
|
|
};
|
|
module_platform_driver(rockchip_pcie_driver);
|
|
|
|
MODULE_AUTHOR("Rockchip Inc");
|
|
MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
|
|
MODULE_LICENSE("GPL v2");
|