1110 lines
30 KiB
C
1110 lines
30 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/phy/phy-qcom-qusb2.h>
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#define QUSB2PHY_PLL 0x0
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#define QUSB2PHY_PLL_TEST 0x04
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#define CLK_REF_SEL BIT(7)
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#define QUSB2PHY_PLL_TUNE 0x08
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#define QUSB2PHY_PLL_USER_CTL1 0x0c
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#define QUSB2PHY_PLL_USER_CTL2 0x10
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#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
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#define QUSB2PHY_PLL_PWR_CTRL 0x18
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/* QUSB2PHY_PLL_STATUS register bits */
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#define PLL_LOCKED BIT(5)
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/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
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#define CORE_READY_STATUS BIT(0)
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/* QUSB2PHY_PORT_POWERDOWN register bits */
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#define CLAMP_N_EN BIT(5)
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#define FREEZIO_N BIT(1)
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#define POWER_DOWN BIT(0)
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/* QUSB2PHY_PWR_CTRL1 register bits */
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#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
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#define PWR_CTRL1_CLAMP_N_EN BIT(1)
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#define QUSB2PHY_REFCLK_ENABLE BIT(0)
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#define PHY_CLK_SCHEME_SEL BIT(0)
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/* QUSB2PHY_INTR_CTRL register bits */
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#define DMSE_INTR_HIGH_SEL BIT(4)
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#define DPSE_INTR_HIGH_SEL BIT(3)
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#define CHG_DET_INTR_EN BIT(2)
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#define DMSE_INTR_EN BIT(1)
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#define DPSE_INTR_EN BIT(0)
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/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
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#define CORE_PLL_EN_FROM_RESET BIT(4)
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#define CORE_RESET BIT(5)
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#define CORE_RESET_MUX BIT(6)
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/* QUSB2PHY_IMP_CTRL1 register bits */
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#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
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#define IMP_RES_OFFSET_SHIFT 0x0
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/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
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#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
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#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
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/* QUSB2PHY_CHG_CONTROL_2 register bits */
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#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
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#define CHG_CTRL2_OFFSET_SHIFT 0x4
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/* QUSB2PHY_PORT_TUNE1 register bits */
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#define HSTX_TRIM_MASK GENMASK(7, 4)
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#define HSTX_TRIM_SHIFT 0x4
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#define PREEMPH_WIDTH_HALF_BIT BIT(2)
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#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
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#define PREEMPHASIS_EN_SHIFT 0x0
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/* QUSB2PHY_PORT_TUNE2 register bits */
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#define HSDISC_TRIM_MASK GENMASK(1, 0)
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#define HSDISC_TRIM_SHIFT 0x0
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#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
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#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
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#define QUSB2PHY_PLL_CMODE 0x2c
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#define QUSB2PHY_PLL_LOCK_DELAY 0x184
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#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
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#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
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#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
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#define QUSB2PHY_PWR_CTRL2 0x214
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#define QUSB2PHY_IMP_CTRL1 0x220
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#define QUSB2PHY_IMP_CTRL2 0x224
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#define QUSB2PHY_CHG_CTRL2 0x23c
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struct qusb2_phy_init_tbl {
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unsigned int offset;
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unsigned int val;
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/*
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* register part of layout ?
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* if yes, then offset gives index in the reg-layout
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*/
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int in_layout;
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};
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#define QUSB2_PHY_INIT_CFG(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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}
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#define QUSB2_PHY_INIT_CFG_L(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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.in_layout = 1, \
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}
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/* set of registers with offsets different per-PHY */
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enum qusb2phy_reg_layout {
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QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
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QUSB2PHY_PLL_STATUS,
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QUSB2PHY_PORT_TUNE1,
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QUSB2PHY_PORT_TUNE2,
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QUSB2PHY_PORT_TUNE3,
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QUSB2PHY_PORT_TUNE4,
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QUSB2PHY_PORT_TUNE5,
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QUSB2PHY_PORT_TEST1,
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QUSB2PHY_PORT_TEST2,
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QUSB2PHY_PORT_POWERDOWN,
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QUSB2PHY_INTR_CTRL,
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};
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static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
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};
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static const unsigned int ipq6018_regs_layout[] = {
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[QUSB2PHY_PLL_STATUS] = 0x38,
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[QUSB2PHY_PORT_TUNE1] = 0x80,
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[QUSB2PHY_PORT_TUNE2] = 0x84,
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[QUSB2PHY_PORT_TUNE3] = 0x88,
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[QUSB2PHY_PORT_TUNE4] = 0x8C,
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[QUSB2PHY_PORT_TUNE5] = 0x90,
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[QUSB2PHY_PORT_TEST1] = 0x98,
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[QUSB2PHY_PORT_TEST2] = 0x9C,
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[QUSB2PHY_PORT_POWERDOWN] = 0xB4,
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[QUSB2PHY_INTR_CTRL] = 0xBC,
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};
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static const unsigned int msm8996_regs_layout[] = {
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[QUSB2PHY_PLL_STATUS] = 0x38,
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[QUSB2PHY_PORT_TUNE1] = 0x80,
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[QUSB2PHY_PORT_TUNE2] = 0x84,
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[QUSB2PHY_PORT_TUNE3] = 0x88,
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[QUSB2PHY_PORT_TUNE4] = 0x8c,
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[QUSB2PHY_PORT_TUNE5] = 0x90,
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[QUSB2PHY_PORT_TEST1] = 0xb8,
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[QUSB2PHY_PORT_TEST2] = 0x9c,
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[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
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[QUSB2PHY_INTR_CTRL] = 0xbc,
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};
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static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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};
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static const unsigned int msm8998_regs_layout[] = {
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[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
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[QUSB2PHY_PLL_STATUS] = 0x1a0,
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[QUSB2PHY_PORT_TUNE1] = 0x23c,
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[QUSB2PHY_PORT_TUNE2] = 0x240,
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[QUSB2PHY_PORT_TUNE3] = 0x244,
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[QUSB2PHY_PORT_TUNE4] = 0x248,
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[QUSB2PHY_PORT_TEST1] = 0x24c,
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[QUSB2PHY_PORT_TEST2] = 0x250,
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[QUSB2PHY_PORT_POWERDOWN] = 0x210,
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[QUSB2PHY_INTR_CTRL] = 0x22c,
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};
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static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
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};
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static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
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};
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static const unsigned int qusb2_v2_regs_layout[] = {
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[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
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[QUSB2PHY_PLL_STATUS] = 0x1a0,
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[QUSB2PHY_PORT_TUNE1] = 0x240,
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[QUSB2PHY_PORT_TUNE2] = 0x244,
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[QUSB2PHY_PORT_TUNE3] = 0x248,
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[QUSB2PHY_PORT_TUNE4] = 0x24c,
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[QUSB2PHY_PORT_TUNE5] = 0x250,
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[QUSB2PHY_PORT_TEST1] = 0x254,
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[QUSB2PHY_PORT_TEST2] = 0x258,
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[QUSB2PHY_PORT_POWERDOWN] = 0x210,
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[QUSB2PHY_INTR_CTRL] = 0x230,
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};
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static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
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QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
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QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
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};
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struct qusb2_phy_cfg {
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const struct qusb2_phy_init_tbl *tbl;
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/* number of entries in the table */
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unsigned int tbl_num;
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/* offset to PHY_CLK_SCHEME register in TCSR map */
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unsigned int clk_scheme_offset;
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/* array of registers with different offsets */
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const unsigned int *regs;
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unsigned int mask_core_ready;
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unsigned int disable_ctrl;
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unsigned int autoresume_en;
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/* true if PHY has PLL_TEST register to select clk_scheme */
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bool has_pll_test;
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/* true if TUNE1 register must be updated by fused value, else TUNE2 */
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bool update_tune1_with_efuse;
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/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
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bool has_pll_override;
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/* true if PHY default clk scheme is single-ended */
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bool se_clk_scheme_default;
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};
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static const struct qusb2_phy_cfg msm8996_phy_cfg = {
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.tbl = msm8996_init_tbl,
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.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
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.regs = msm8996_regs_layout,
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.has_pll_test = true,
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.se_clk_scheme_default = true,
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.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(3),
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};
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static const struct qusb2_phy_cfg msm8998_phy_cfg = {
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.tbl = msm8998_init_tbl,
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.tbl_num = ARRAY_SIZE(msm8998_init_tbl),
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.regs = msm8998_regs_layout,
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.disable_ctrl = POWER_DOWN,
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.mask_core_ready = CORE_READY_STATUS,
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.has_pll_override = true,
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.se_clk_scheme_default = true,
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.autoresume_en = BIT(0),
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.update_tune1_with_efuse = true,
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};
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static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
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.tbl = ipq6018_init_tbl,
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.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
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.regs = ipq6018_regs_layout,
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.disable_ctrl = POWER_DOWN,
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.mask_core_ready = PLL_LOCKED,
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/* autoresume not used */
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.autoresume_en = BIT(0),
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};
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static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
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.tbl = qusb2_v2_init_tbl,
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.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
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.regs = qusb2_v2_regs_layout,
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.disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
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POWER_DOWN),
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.mask_core_ready = CORE_READY_STATUS,
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.has_pll_override = true,
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.se_clk_scheme_default = true,
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.autoresume_en = BIT(0),
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.update_tune1_with_efuse = true,
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};
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static const struct qusb2_phy_cfg sdm660_phy_cfg = {
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.tbl = msm8996_init_tbl,
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.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
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.regs = msm8996_regs_layout,
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.has_pll_test = true,
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.se_clk_scheme_default = false,
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.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(3),
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};
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static const struct qusb2_phy_cfg sm6115_phy_cfg = {
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.tbl = sm6115_init_tbl,
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.tbl_num = ARRAY_SIZE(sm6115_init_tbl),
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.regs = msm8996_regs_layout,
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.has_pll_test = true,
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.se_clk_scheme_default = true,
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.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(3),
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};
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static const char * const qusb2_phy_vreg_names[] = {
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"vdd", "vdda-pll", "vdda-phy-dpdm",
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};
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#define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
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/* struct override_param - structure holding qusb2 v2 phy overriding param
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* set override true if the device tree property exists and read and assign
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* to value
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*/
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struct override_param {
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bool override;
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u8 value;
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};
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/*struct override_params - structure holding qusb2 v2 phy overriding params
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* @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
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* @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
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* @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
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* @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
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* @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
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* @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
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* @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
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*/
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struct override_params {
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struct override_param imp_res_offset;
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struct override_param hstx_trim;
|
|
struct override_param preemphasis;
|
|
struct override_param preemphasis_width;
|
|
struct override_param bias_ctrl;
|
|
struct override_param charge_ctrl;
|
|
struct override_param hsdisc_trim;
|
|
};
|
|
|
|
/**
|
|
* struct qusb2_phy - structure holding qusb2 phy attributes
|
|
*
|
|
* @phy: generic phy
|
|
* @base: iomapped memory space for qubs2 phy
|
|
*
|
|
* @cfg_ahb_clk: AHB2PHY interface clock
|
|
* @ref_clk: phy reference clock
|
|
* @iface_clk: phy interface clock
|
|
* @phy_reset: phy reset control
|
|
* @vregs: regulator supplies bulk data
|
|
*
|
|
* @tcsr: TCSR syscon register map
|
|
* @cell: nvmem cell containing phy tuning value
|
|
*
|
|
* @overrides: pointer to structure for all overriding tuning params
|
|
*
|
|
* @cfg: phy config data
|
|
* @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
|
|
* @phy_initialized: indicate if PHY has been initialized
|
|
* @mode: current PHY mode
|
|
*/
|
|
struct qusb2_phy {
|
|
struct phy *phy;
|
|
void __iomem *base;
|
|
|
|
struct clk *cfg_ahb_clk;
|
|
struct clk *ref_clk;
|
|
struct clk *iface_clk;
|
|
struct reset_control *phy_reset;
|
|
struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
|
|
|
|
struct regmap *tcsr;
|
|
struct nvmem_cell *cell;
|
|
|
|
struct override_params overrides;
|
|
|
|
const struct qusb2_phy_cfg *cfg;
|
|
bool has_se_clk_scheme;
|
|
bool phy_initialized;
|
|
enum phy_mode mode;
|
|
};
|
|
|
|
static inline void qusb2_write_mask(void __iomem *base, u32 offset,
|
|
u32 val, u32 mask)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(base + offset);
|
|
reg &= ~mask;
|
|
reg |= val & mask;
|
|
writel(reg, base + offset);
|
|
|
|
/* Ensure above write is completed */
|
|
readl(base + offset);
|
|
}
|
|
|
|
static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(base + offset);
|
|
reg |= val;
|
|
writel(reg, base + offset);
|
|
|
|
/* Ensure above write is completed */
|
|
readl(base + offset);
|
|
}
|
|
|
|
static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(base + offset);
|
|
reg &= ~val;
|
|
writel(reg, base + offset);
|
|
|
|
/* Ensure above write is completed */
|
|
readl(base + offset);
|
|
}
|
|
|
|
static inline
|
|
void qcom_qusb2_phy_configure(void __iomem *base,
|
|
const unsigned int *regs,
|
|
const struct qusb2_phy_init_tbl tbl[], int num)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
if (tbl[i].in_layout)
|
|
writel(tbl[i].val, base + regs[tbl[i].offset]);
|
|
else
|
|
writel(tbl[i].val, base + tbl[i].offset);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Update board specific PHY tuning override values if specified from
|
|
* device tree.
|
|
*/
|
|
static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
|
|
{
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
struct override_params *or = &qphy->overrides;
|
|
|
|
if (or->imp_res_offset.override)
|
|
qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
|
|
or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
|
|
IMP_RES_OFFSET_MASK);
|
|
|
|
if (or->bias_ctrl.override)
|
|
qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
|
|
or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
|
|
BIAS_CTRL2_RES_OFFSET_MASK);
|
|
|
|
if (or->charge_ctrl.override)
|
|
qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
|
|
or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
|
|
CHG_CTRL2_OFFSET_MASK);
|
|
|
|
if (or->hstx_trim.override)
|
|
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
|
|
or->hstx_trim.value << HSTX_TRIM_SHIFT,
|
|
HSTX_TRIM_MASK);
|
|
|
|
if (or->preemphasis.override)
|
|
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
|
|
or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
|
|
PREEMPHASIS_EN_MASK);
|
|
|
|
if (or->preemphasis_width.override) {
|
|
if (or->preemphasis_width.value ==
|
|
QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
|
|
qusb2_setbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PORT_TUNE1],
|
|
PREEMPH_WIDTH_HALF_BIT);
|
|
else
|
|
qusb2_clrbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PORT_TUNE1],
|
|
PREEMPH_WIDTH_HALF_BIT);
|
|
}
|
|
|
|
if (or->hsdisc_trim.override)
|
|
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
|
|
or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
|
|
HSDISC_TRIM_MASK);
|
|
}
|
|
|
|
/*
|
|
* Fetches HS Tx tuning value from nvmem and sets the
|
|
* QUSB2PHY_PORT_TUNE1/2 register.
|
|
* For error case, skip setting the value and use the default value.
|
|
*/
|
|
static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
|
|
{
|
|
struct device *dev = &qphy->phy->dev;
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
u8 *val, hstx_trim;
|
|
|
|
/* efuse register is optional */
|
|
if (!qphy->cell)
|
|
return;
|
|
|
|
/*
|
|
* Read efuse register having TUNE2/1 parameter's high nibble.
|
|
* If efuse register shows value as 0x0 (indicating value is not
|
|
* fused), or if we fail to find a valid efuse register setting,
|
|
* then use default value for high nibble that we have already
|
|
* set while configuring the phy.
|
|
*/
|
|
val = nvmem_cell_read(qphy->cell, NULL);
|
|
if (IS_ERR(val)) {
|
|
dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
|
|
return;
|
|
}
|
|
hstx_trim = val[0];
|
|
kfree(val);
|
|
if (!hstx_trim) {
|
|
dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
|
|
return;
|
|
}
|
|
|
|
/* Fused TUNE1/2 value is the higher nibble only */
|
|
if (cfg->update_tune1_with_efuse)
|
|
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
|
|
hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
|
|
else
|
|
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
|
|
hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
|
|
}
|
|
|
|
static int qusb2_phy_set_mode(struct phy *phy,
|
|
enum phy_mode mode, int submode)
|
|
{
|
|
struct qusb2_phy *qphy = phy_get_drvdata(phy);
|
|
|
|
qphy->mode = mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
|
|
{
|
|
struct qusb2_phy *qphy = dev_get_drvdata(dev);
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
u32 intr_mask;
|
|
|
|
dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
|
|
|
|
if (!qphy->phy_initialized) {
|
|
dev_vdbg(dev, "PHY not initialized, bailing out\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Enable DP/DM interrupts to detect line state changes based on current
|
|
* speed. In other words, enable the triggers _opposite_ of what the
|
|
* current D+/D- levels are e.g. if currently D+ high, D- low
|
|
* (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
|
|
*/
|
|
intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
|
|
switch (qphy->mode) {
|
|
case PHY_MODE_USB_HOST_HS:
|
|
case PHY_MODE_USB_HOST_FS:
|
|
case PHY_MODE_USB_DEVICE_HS:
|
|
case PHY_MODE_USB_DEVICE_FS:
|
|
intr_mask |= DMSE_INTR_HIGH_SEL;
|
|
break;
|
|
case PHY_MODE_USB_HOST_LS:
|
|
case PHY_MODE_USB_DEVICE_LS:
|
|
intr_mask |= DPSE_INTR_HIGH_SEL;
|
|
break;
|
|
default:
|
|
/* No device connected, enable both DP/DM high interrupt */
|
|
intr_mask |= DMSE_INTR_HIGH_SEL;
|
|
intr_mask |= DPSE_INTR_HIGH_SEL;
|
|
break;
|
|
}
|
|
|
|
writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
|
|
|
|
/* hold core PLL into reset */
|
|
if (cfg->has_pll_override) {
|
|
qusb2_setbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
|
|
CORE_PLL_EN_FROM_RESET | CORE_RESET |
|
|
CORE_RESET_MUX);
|
|
}
|
|
|
|
/* enable phy auto-resume only if device is connected on bus */
|
|
if (qphy->mode != PHY_MODE_INVALID) {
|
|
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
|
|
cfg->autoresume_en);
|
|
/* Autoresume bit has to be toggled in order to enable it */
|
|
qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
|
|
cfg->autoresume_en);
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
|
|
{
|
|
struct qusb2_phy *qphy = dev_get_drvdata(dev);
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
int ret;
|
|
|
|
dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
|
|
|
|
if (!qphy->phy_initialized) {
|
|
dev_vdbg(dev, "PHY not initialized, bailing out\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = clk_prepare_enable(qphy->iface_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable iface_clk, %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(qphy->cfg_ahb_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
|
|
goto disable_iface_clk;
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme) {
|
|
ret = clk_prepare_enable(qphy->ref_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable ref clk, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
}
|
|
|
|
writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
|
|
|
|
/* bring core PLL out of reset */
|
|
if (cfg->has_pll_override) {
|
|
qusb2_clrbits(qphy->base,
|
|
cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
|
|
CORE_RESET | CORE_RESET_MUX);
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_ahb_clk:
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
disable_iface_clk:
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qusb2_phy_init(struct phy *phy)
|
|
{
|
|
struct qusb2_phy *qphy = phy_get_drvdata(phy);
|
|
const struct qusb2_phy_cfg *cfg = qphy->cfg;
|
|
unsigned int val = 0;
|
|
unsigned int clk_scheme;
|
|
int ret;
|
|
|
|
dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
|
|
|
|
/* turn on regulator supplies */
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(qphy->iface_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
|
|
goto poweroff_phy;
|
|
}
|
|
|
|
/* enable ahb interface clock to program phy */
|
|
ret = clk_prepare_enable(qphy->cfg_ahb_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
|
|
goto disable_iface_clk;
|
|
}
|
|
|
|
/* Perform phy reset */
|
|
ret = reset_control_assert(qphy->phy_reset);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
|
|
/* 100 us delay to keep PHY in reset mode */
|
|
usleep_range(100, 150);
|
|
|
|
ret = reset_control_deassert(qphy->phy_reset);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
|
|
goto disable_ahb_clk;
|
|
}
|
|
|
|
/* Disable the PHY */
|
|
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
qphy->cfg->disable_ctrl);
|
|
|
|
if (cfg->has_pll_test) {
|
|
/* save reset value to override reference clock scheme later */
|
|
val = readl(qphy->base + QUSB2PHY_PLL_TEST);
|
|
}
|
|
|
|
qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
|
|
cfg->tbl_num);
|
|
|
|
/* Override board specific PHY tuning values */
|
|
qusb2_phy_override_phy_params(qphy);
|
|
|
|
/* Set efuse value for tuning the PHY */
|
|
qusb2_phy_set_tune2_param(qphy);
|
|
|
|
/* Enable the PHY */
|
|
qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
POWER_DOWN);
|
|
|
|
/* Required to get phy pll lock successfully */
|
|
usleep_range(150, 160);
|
|
|
|
/*
|
|
* Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
|
|
* register in the TCSR so, if there's none, use the default
|
|
* value hardcoded in the configuration.
|
|
*/
|
|
qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
|
|
|
|
/*
|
|
* read TCSR_PHY_CLK_SCHEME register to check if single-ended
|
|
* clock scheme is selected. If yes, then disable differential
|
|
* ref_clk and use single-ended clock, otherwise use differential
|
|
* ref_clk only.
|
|
*/
|
|
if (qphy->tcsr) {
|
|
ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
|
|
&clk_scheme);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to read clk scheme reg\n");
|
|
goto assert_phy_reset;
|
|
}
|
|
|
|
/* is it a differential clock scheme ? */
|
|
if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
|
|
dev_vdbg(&phy->dev, "%s(): select differential clk\n",
|
|
__func__);
|
|
qphy->has_se_clk_scheme = false;
|
|
} else {
|
|
dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
|
|
__func__);
|
|
}
|
|
}
|
|
|
|
if (!qphy->has_se_clk_scheme) {
|
|
ret = clk_prepare_enable(qphy->ref_clk);
|
|
if (ret) {
|
|
dev_err(&phy->dev, "failed to enable ref clk, %d\n",
|
|
ret);
|
|
goto assert_phy_reset;
|
|
}
|
|
}
|
|
|
|
if (cfg->has_pll_test) {
|
|
if (!qphy->has_se_clk_scheme)
|
|
val &= ~CLK_REF_SEL;
|
|
else
|
|
val |= CLK_REF_SEL;
|
|
|
|
writel(val, qphy->base + QUSB2PHY_PLL_TEST);
|
|
|
|
/* ensure above write is through */
|
|
readl(qphy->base + QUSB2PHY_PLL_TEST);
|
|
}
|
|
|
|
/* Required to get phy pll lock successfully */
|
|
usleep_range(100, 110);
|
|
|
|
val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
|
|
if (!(val & cfg->mask_core_ready)) {
|
|
dev_err(&phy->dev,
|
|
"QUSB2PHY pll lock failed: status reg = %x\n", val);
|
|
ret = -EBUSY;
|
|
goto disable_ref_clk;
|
|
}
|
|
qphy->phy_initialized = true;
|
|
|
|
return 0;
|
|
|
|
disable_ref_clk:
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
assert_phy_reset:
|
|
reset_control_assert(qphy->phy_reset);
|
|
disable_ahb_clk:
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
disable_iface_clk:
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
poweroff_phy:
|
|
regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qusb2_phy_exit(struct phy *phy)
|
|
{
|
|
struct qusb2_phy *qphy = phy_get_drvdata(phy);
|
|
|
|
/* Disable the PHY */
|
|
qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
|
|
qphy->cfg->disable_ctrl);
|
|
|
|
if (!qphy->has_se_clk_scheme)
|
|
clk_disable_unprepare(qphy->ref_clk);
|
|
|
|
reset_control_assert(qphy->phy_reset);
|
|
|
|
clk_disable_unprepare(qphy->cfg_ahb_clk);
|
|
clk_disable_unprepare(qphy->iface_clk);
|
|
|
|
regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
|
|
|
|
qphy->phy_initialized = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_ops qusb2_phy_gen_ops = {
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.init = qusb2_phy_init,
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.exit = qusb2_phy_exit,
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.set_mode = qusb2_phy_set_mode,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id qusb2_phy_of_match_table[] = {
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{
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.compatible = "qcom,ipq6018-qusb2-phy",
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.data = &ipq6018_phy_cfg,
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}, {
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.compatible = "qcom,ipq8074-qusb2-phy",
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.data = &msm8996_phy_cfg,
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}, {
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.compatible = "qcom,ipq9574-qusb2-phy",
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.data = &ipq6018_phy_cfg,
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}, {
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.compatible = "qcom,msm8953-qusb2-phy",
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.data = &msm8996_phy_cfg,
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}, {
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.compatible = "qcom,msm8996-qusb2-phy",
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.data = &msm8996_phy_cfg,
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}, {
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.compatible = "qcom,msm8998-qusb2-phy",
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.data = &msm8998_phy_cfg,
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}, {
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.compatible = "qcom,qcm2290-qusb2-phy",
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.data = &sm6115_phy_cfg,
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}, {
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.compatible = "qcom,sdm660-qusb2-phy",
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.data = &sdm660_phy_cfg,
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}, {
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.compatible = "qcom,sm4250-qusb2-phy",
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.data = &sm6115_phy_cfg,
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}, {
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.compatible = "qcom,sm6115-qusb2-phy",
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.data = &sm6115_phy_cfg,
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}, {
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/*
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* Deprecated. Only here to support legacy device
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* trees that didn't include "qcom,qusb2-v2-phy"
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*/
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.compatible = "qcom,sdm845-qusb2-phy",
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.data = &qusb2_v2_phy_cfg,
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}, {
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.compatible = "qcom,qusb2-v2-phy",
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.data = &qusb2_v2_phy_cfg,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
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static const struct dev_pm_ops qusb2_phy_pm_ops = {
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SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
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qusb2_phy_runtime_resume, NULL)
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};
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|
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static int qusb2_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct qusb2_phy *qphy;
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struct phy_provider *phy_provider;
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struct phy *generic_phy;
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int ret, i;
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int num;
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u32 value;
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struct override_params *or;
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|
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qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
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if (!qphy)
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return -ENOMEM;
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or = &qphy->overrides;
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qphy->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(qphy->base))
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return PTR_ERR(qphy->base);
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qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
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if (IS_ERR(qphy->cfg_ahb_clk))
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return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk),
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"failed to get cfg ahb clk\n");
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|
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qphy->ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(qphy->ref_clk))
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return dev_err_probe(dev, PTR_ERR(qphy->ref_clk),
|
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"failed to get ref clk\n");
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|
|
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qphy->iface_clk = devm_clk_get_optional(dev, "iface");
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if (IS_ERR(qphy->iface_clk))
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return PTR_ERR(qphy->iface_clk);
|
|
|
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qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
|
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if (IS_ERR(qphy->phy_reset)) {
|
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dev_err(dev, "failed to get phy core reset\n");
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return PTR_ERR(qphy->phy_reset);
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}
|
|
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num = ARRAY_SIZE(qphy->vregs);
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for (i = 0; i < num; i++)
|
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qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
|
|
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ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
|
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if (ret)
|
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return dev_err_probe(dev, ret,
|
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"failed to get regulator supplies\n");
|
|
|
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/* Get the specific init parameters of QMP phy */
|
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qphy->cfg = of_device_get_match_data(dev);
|
|
|
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qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
|
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"qcom,tcsr-syscon");
|
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if (IS_ERR(qphy->tcsr)) {
|
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dev_dbg(dev, "failed to lookup TCSR regmap\n");
|
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qphy->tcsr = NULL;
|
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}
|
|
|
|
qphy->cell = devm_nvmem_cell_get(dev, NULL);
|
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if (IS_ERR(qphy->cell)) {
|
|
if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
qphy->cell = NULL;
|
|
dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
|
|
}
|
|
|
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if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
|
|
&value)) {
|
|
or->imp_res_offset.value = (u8)value;
|
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or->imp_res_offset.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
|
|
&value)) {
|
|
or->bias_ctrl.value = (u8)value;
|
|
or->bias_ctrl.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
|
|
&value)) {
|
|
or->charge_ctrl.value = (u8)value;
|
|
or->charge_ctrl.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
|
|
&value)) {
|
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or->hstx_trim.value = (u8)value;
|
|
or->hstx_trim.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
|
|
&value)) {
|
|
or->preemphasis.value = (u8)value;
|
|
or->preemphasis.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
|
|
&value)) {
|
|
or->preemphasis_width.value = (u8)value;
|
|
or->preemphasis_width.override = true;
|
|
}
|
|
|
|
if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
|
|
&value)) {
|
|
or->hsdisc_trim.value = (u8)value;
|
|
or->hsdisc_trim.override = true;
|
|
}
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
/*
|
|
* Prevent runtime pm from being ON by default. Users can enable
|
|
* it using power/control in sysfs.
|
|
*/
|
|
pm_runtime_forbid(dev);
|
|
|
|
generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
|
|
if (IS_ERR(generic_phy)) {
|
|
ret = PTR_ERR(generic_phy);
|
|
dev_err(dev, "failed to create phy, %d\n", ret);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
qphy->phy = generic_phy;
|
|
|
|
dev_set_drvdata(dev, qphy);
|
|
phy_set_drvdata(generic_phy, qphy);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (!IS_ERR(phy_provider))
|
|
dev_info(dev, "Registered Qcom-QUSB2 phy\n");
|
|
else
|
|
pm_runtime_disable(dev);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver qusb2_phy_driver = {
|
|
.probe = qusb2_phy_probe,
|
|
.driver = {
|
|
.name = "qcom-qusb2-phy",
|
|
.pm = &qusb2_phy_pm_ops,
|
|
.of_match_table = qusb2_phy_of_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qusb2_phy_driver);
|
|
|
|
MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
|
|
MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|