547 lines
14 KiB
C
547 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* AXP20x pinctrl and GPIO driver
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*
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* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
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* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/axp20x.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#define AXP20X_GPIO_FUNCTIONS 0x7
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#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
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#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
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#define AXP20X_GPIO_FUNCTION_INPUT 2
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#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
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#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
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#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
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#define AXP20X_GPIO3_FUNCTION_INPUT 4
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#define AXP20X_FUNC_GPIO_OUT 0
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#define AXP20X_FUNC_GPIO_IN 1
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#define AXP20X_FUNC_LDO 2
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#define AXP20X_FUNC_ADC 3
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#define AXP20X_FUNCS_NB 4
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#define AXP20X_MUX_GPIO_OUT 0
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#define AXP20X_MUX_GPIO_IN BIT(1)
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#define AXP20X_MUX_ADC BIT(2)
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#define AXP813_MUX_ADC (BIT(2) | BIT(0))
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struct axp20x_pctrl_desc {
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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/* Stores the pins supporting LDO function. Bit offset is pin number. */
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u8 ldo_mask;
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/* Stores the pins supporting ADC function. Bit offset is pin number. */
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u8 adc_mask;
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u8 gpio_status_offset;
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u8 adc_mux;
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};
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struct axp20x_pinctrl_function {
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const char *name;
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unsigned int muxval;
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const char **groups;
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unsigned int ngroups;
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};
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struct axp20x_pctl {
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struct gpio_chip chip;
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struct regmap *regmap;
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struct pinctrl_dev *pctl_dev;
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struct device *dev;
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const struct axp20x_pctrl_desc *desc;
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struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
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};
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static const struct pinctrl_pin_desc axp209_pins[] = {
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PINCTRL_PIN(0, "GPIO0"),
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PINCTRL_PIN(1, "GPIO1"),
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PINCTRL_PIN(2, "GPIO2"),
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PINCTRL_PIN(3, "GPIO3"),
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};
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static const struct pinctrl_pin_desc axp22x_pins[] = {
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PINCTRL_PIN(0, "GPIO0"),
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PINCTRL_PIN(1, "GPIO1"),
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};
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static const struct axp20x_pctrl_desc axp20x_data = {
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.pins = axp209_pins,
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.npins = ARRAY_SIZE(axp209_pins),
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.ldo_mask = BIT(0) | BIT(1),
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.adc_mask = BIT(0) | BIT(1),
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.gpio_status_offset = 4,
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.adc_mux = AXP20X_MUX_ADC,
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};
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static const struct axp20x_pctrl_desc axp22x_data = {
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.pins = axp22x_pins,
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.npins = ARRAY_SIZE(axp22x_pins),
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.ldo_mask = BIT(0) | BIT(1),
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.gpio_status_offset = 0,
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};
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static const struct axp20x_pctrl_desc axp813_data = {
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.pins = axp22x_pins,
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.npins = ARRAY_SIZE(axp22x_pins),
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.ldo_mask = BIT(0) | BIT(1),
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.adc_mask = BIT(0),
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.gpio_status_offset = 0,
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.adc_mux = AXP813_MUX_ADC,
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};
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static int axp20x_gpio_get_reg(unsigned int offset)
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{
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switch (offset) {
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case 0:
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return AXP20X_GPIO0_CTRL;
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case 1:
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return AXP20X_GPIO1_CTRL;
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case 2:
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return AXP20X_GPIO2_CTRL;
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}
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return -EINVAL;
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}
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static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
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{
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return pinctrl_gpio_direction_input(chip->base + offset);
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}
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static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct axp20x_pctl *pctl = gpiochip_get_data(chip);
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unsigned int val;
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int ret;
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/* AXP209 has GPIO3 status sharing the settings register */
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if (offset == 3) {
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ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
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if (ret)
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return ret;
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return !!(val & BIT(0));
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}
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ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
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if (ret)
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return ret;
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return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
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}
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static int axp20x_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct axp20x_pctl *pctl = gpiochip_get_data(chip);
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unsigned int val;
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int reg, ret;
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/* AXP209 GPIO3 settings have a different layout */
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if (offset == 3) {
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ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
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if (ret)
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return ret;
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if (val & AXP20X_GPIO3_FUNCTION_INPUT)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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reg = axp20x_gpio_get_reg(offset);
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if (reg < 0)
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return reg;
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ret = regmap_read(pctl->regmap, reg, &val);
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if (ret)
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return ret;
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/*
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* This shouldn't really happen if the pin is in use already,
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* or if it's not in use yet, it doesn't matter since we're
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* going to change the value soon anyway. Default to output.
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*/
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if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
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return GPIO_LINE_DIRECTION_OUT;
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/*
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* The GPIO directions are the three lowest values.
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* 2 is input, 0 and 1 are output
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*/
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if (val & 2)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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chip->set(chip, offset, value);
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return 0;
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}
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static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct axp20x_pctl *pctl = gpiochip_get_data(chip);
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int reg;
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/* AXP209 has GPIO3 status sharing the settings register */
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if (offset == 3) {
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regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
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AXP20X_GPIO3_FUNCTIONS,
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value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
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AXP20X_GPIO3_FUNCTION_OUT_LOW);
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return;
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}
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reg = axp20x_gpio_get_reg(offset);
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if (reg < 0)
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return;
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regmap_update_bits(pctl->regmap, reg,
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AXP20X_GPIO_FUNCTIONS,
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value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
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AXP20X_GPIO_FUNCTION_OUT_LOW);
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}
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static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
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u8 config)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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int reg;
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/* AXP209 GPIO3 settings have a different layout */
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if (offset == 3) {
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return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
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AXP20X_GPIO3_FUNCTIONS,
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config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
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AXP20X_GPIO3_FUNCTION_INPUT);
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}
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reg = axp20x_gpio_get_reg(offset);
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if (reg < 0)
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return reg;
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return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
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config);
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}
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static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return ARRAY_SIZE(pctl->funcs);
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}
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static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->funcs[selector].name;
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}
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static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const char * const **groups,
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unsigned int *num_groups)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctl->funcs[selector].groups;
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*num_groups = pctl->funcs[selector].ngroups;
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return 0;
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}
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static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function, unsigned int group)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned int mask;
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/* Every pin supports GPIO_OUT and GPIO_IN functions */
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if (function <= AXP20X_FUNC_GPIO_IN)
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return axp20x_pmx_set(pctldev, group,
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pctl->funcs[function].muxval);
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if (function == AXP20X_FUNC_LDO)
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mask = pctl->desc->ldo_mask;
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else
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mask = pctl->desc->adc_mask;
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if (!(BIT(group) & mask))
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return -EINVAL;
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/*
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* We let the regulator framework handle the LDO muxing as muxing bits
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* are basically also regulators on/off bits. It's better not to enforce
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* any state of the regulator when selecting LDO mux so that we don't
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* interfere with the regulator driver.
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*/
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if (function == AXP20X_FUNC_LDO)
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return 0;
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return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
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}
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static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset, bool input)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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if (input)
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return axp20x_pmx_set(pctldev, offset,
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pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
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return axp20x_pmx_set(pctldev, offset,
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pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
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}
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static const struct pinmux_ops axp20x_pmx_ops = {
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.get_functions_count = axp20x_pmx_func_cnt,
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.get_function_name = axp20x_pmx_func_name,
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.get_function_groups = axp20x_pmx_func_groups,
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.set_mux = axp20x_pmx_set_mux,
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.gpio_set_direction = axp20x_pmx_gpio_set_direction,
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.strict = true,
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};
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static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->desc->npins;
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}
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static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
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const unsigned int **pins, unsigned int *num_pins)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*pins = (unsigned int *)&pctl->desc->pins[selector];
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*num_pins = 1;
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return 0;
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}
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static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->desc->pins[selector].name;
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}
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static const struct pinctrl_ops axp20x_pctrl_ops = {
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinconf_generic_dt_free_map,
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.get_groups_count = axp20x_groups_cnt,
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.get_group_name = axp20x_group_name,
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.get_group_pins = axp20x_group_pins,
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};
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static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
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unsigned int mask_len,
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struct axp20x_pinctrl_function *func,
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const struct pinctrl_pin_desc *pins)
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{
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unsigned long int mask_cpy = mask;
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const char **group;
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unsigned int ngroups = hweight8(mask);
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int bit;
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func->ngroups = ngroups;
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if (func->ngroups > 0) {
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func->groups = devm_kcalloc(dev,
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ngroups, sizeof(const char *),
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GFP_KERNEL);
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if (!func->groups)
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return -ENOMEM;
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group = func->groups;
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for_each_set_bit(bit, &mask_cpy, mask_len) {
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*group = pins[bit].name;
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group++;
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}
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}
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return 0;
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}
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static int axp20x_build_funcs_groups(struct platform_device *pdev)
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{
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struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
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int i, ret, pin, npins = pctl->desc->npins;
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pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
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pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
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pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
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pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
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pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
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/*
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* Muxval for LDO is useless as we won't use it.
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* See comment in axp20x_pmx_set_mux.
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*/
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pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
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pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
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/* Every pin supports GPIO_OUT and GPIO_IN functions */
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for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
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pctl->funcs[i].ngroups = npins;
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pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
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npins, sizeof(char *),
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GFP_KERNEL);
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if (!pctl->funcs[i].groups)
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return -ENOMEM;
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for (pin = 0; pin < npins; pin++)
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pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
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}
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ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
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npins, &pctl->funcs[AXP20X_FUNC_LDO],
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pctl->desc->pins);
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if (ret)
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return ret;
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ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
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npins, &pctl->funcs[AXP20X_FUNC_ADC],
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pctl->desc->pins);
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if (ret)
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return ret;
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return 0;
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}
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static const struct of_device_id axp20x_pctl_match[] = {
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{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
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{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
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{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
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{ }
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};
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MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
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static int axp20x_pctl_probe(struct platform_device *pdev)
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{
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struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
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struct axp20x_pctl *pctl;
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struct device *dev = &pdev->dev;
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struct pinctrl_desc *pctrl_desc;
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int ret;
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if (!of_device_is_available(pdev->dev.of_node))
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return -ENODEV;
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if (!axp20x) {
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dev_err(&pdev->dev, "Parent drvdata not set\n");
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return -EINVAL;
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}
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pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
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if (!pctl)
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return -ENOMEM;
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pctl->chip.base = -1;
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pctl->chip.can_sleep = true;
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pctl->chip.request = gpiochip_generic_request;
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pctl->chip.free = gpiochip_generic_free;
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pctl->chip.parent = &pdev->dev;
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pctl->chip.label = dev_name(&pdev->dev);
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pctl->chip.owner = THIS_MODULE;
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pctl->chip.get = axp20x_gpio_get;
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pctl->chip.get_direction = axp20x_gpio_get_direction;
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pctl->chip.set = axp20x_gpio_set;
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pctl->chip.direction_input = axp20x_gpio_input;
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pctl->chip.direction_output = axp20x_gpio_output;
|
|
|
|
pctl->desc = of_device_get_match_data(dev);
|
|
|
|
pctl->chip.ngpio = pctl->desc->npins;
|
|
|
|
pctl->regmap = axp20x->regmap;
|
|
pctl->dev = &pdev->dev;
|
|
|
|
platform_set_drvdata(pdev, pctl);
|
|
|
|
ret = axp20x_build_funcs_groups(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to build groups\n");
|
|
return ret;
|
|
}
|
|
|
|
pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
|
|
if (!pctrl_desc)
|
|
return -ENOMEM;
|
|
|
|
pctrl_desc->name = dev_name(&pdev->dev);
|
|
pctrl_desc->owner = THIS_MODULE;
|
|
pctrl_desc->pins = pctl->desc->pins;
|
|
pctrl_desc->npins = pctl->desc->npins;
|
|
pctrl_desc->pctlops = &axp20x_pctrl_ops;
|
|
pctrl_desc->pmxops = &axp20x_pmx_ops;
|
|
|
|
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
|
|
if (IS_ERR(pctl->pctl_dev)) {
|
|
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
|
return PTR_ERR(pctl->pctl_dev);
|
|
}
|
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register GPIO chip\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
|
|
pctl->desc->pins->number,
|
|
pctl->desc->pins->number,
|
|
pctl->desc->npins);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to add pin range\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver axp20x_pctl_driver = {
|
|
.probe = axp20x_pctl_probe,
|
|
.driver = {
|
|
.name = "axp20x-gpio",
|
|
.of_match_table = axp20x_pctl_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(axp20x_pctl_driver);
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
|
|
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
|
|
MODULE_LICENSE("GPL");
|