33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
|
|
/*
|
|
* Copyright (c) 2022 MediaTek Inc.
|
|
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H
|
|
#define _DT_BINDINGS_POWER_MT8186_POWER_H
|
|
|
|
#define MT8186_POWER_DOMAIN_MFG0 0
|
|
#define MT8186_POWER_DOMAIN_MFG1 1
|
|
#define MT8186_POWER_DOMAIN_MFG2 2
|
|
#define MT8186_POWER_DOMAIN_MFG3 3
|
|
#define MT8186_POWER_DOMAIN_SSUSB 4
|
|
#define MT8186_POWER_DOMAIN_SSUSB_P1 5
|
|
#define MT8186_POWER_DOMAIN_DIS 6
|
|
#define MT8186_POWER_DOMAIN_IMG 7
|
|
#define MT8186_POWER_DOMAIN_IMG2 8
|
|
#define MT8186_POWER_DOMAIN_IPE 9
|
|
#define MT8186_POWER_DOMAIN_CAM 10
|
|
#define MT8186_POWER_DOMAIN_CAM_RAWA 11
|
|
#define MT8186_POWER_DOMAIN_CAM_RAWB 12
|
|
#define MT8186_POWER_DOMAIN_VENC 13
|
|
#define MT8186_POWER_DOMAIN_VDEC 14
|
|
#define MT8186_POWER_DOMAIN_WPE 15
|
|
#define MT8186_POWER_DOMAIN_CONN_ON 16
|
|
#define MT8186_POWER_DOMAIN_CSIRX_TOP 17
|
|
#define MT8186_POWER_DOMAIN_ADSP_AO 18
|
|
#define MT8186_POWER_DOMAIN_ADSP_INFRA 19
|
|
#define MT8186_POWER_DOMAIN_ADSP_TOP 20
|
|
|
|
#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */
|