121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA core driver
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#ifndef _DW_EDMA_H
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#define _DW_EDMA_H
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#define EDMA_MAX_WR_CH 8
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#define EDMA_MAX_RD_CH 8
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struct dw_edma;
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struct dw_edma_region {
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u64 paddr;
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union {
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void *mem;
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void __iomem *io;
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} vaddr;
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size_t sz;
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};
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/**
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* struct dw_edma_core_ops - platform-specific eDMA methods
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* @irq_vector: Get IRQ number of the passed eDMA channel. Note the
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* method accepts the channel id in the end-to-end
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* numbering with the eDMA write channels being placed
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* first in the row.
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* @pci_address: Get PCIe bus address corresponding to the passed CPU
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* address. Note there is no need in specifying this
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* function if the address translation is performed by
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* the DW PCIe RP/EP controller with the DW eDMA device in
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* subject and DMA_BYPASS isn't set for all the outbound
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* iATU windows. That will be done by the controller
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* automatically.
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*/
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struct dw_edma_plat_ops {
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int (*irq_vector)(struct device *dev, unsigned int nr);
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u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr);
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};
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enum dw_edma_map_format {
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EDMA_MF_EDMA_LEGACY = 0x0,
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EDMA_MF_EDMA_UNROLL = 0x1,
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EDMA_MF_HDMA_COMPAT = 0x5,
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EDMA_MF_HDMA_NATIVE = 0x7,
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};
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/**
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* enum dw_edma_chip_flags - Flags specific to an eDMA chip
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* @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
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*/
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enum dw_edma_chip_flags {
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DW_EDMA_CHIP_LOCAL = BIT(0),
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};
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/**
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* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
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* @dev: struct device of the eDMA controller
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* @id: instance ID
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* @nr_irqs: total number of DMA IRQs
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* @ops DMA channel to IRQ number mapping
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* @flags dw_edma_chip_flags
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* @reg_base DMA register base address
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* @ll_wr_cnt DMA write link list count
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* @ll_rd_cnt DMA read link list count
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* @rg_region DMA register region
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* @ll_region_wr DMA descriptor link list memory for write channel
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* @ll_region_rd DMA descriptor link list memory for read channel
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* @dt_region_wr DMA data memory for write channel
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* @dt_region_rd DMA data memory for read channel
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* @mf DMA register map format
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* @dw: struct dw_edma that is filled by dw_edma_probe()
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*/
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struct dw_edma_chip {
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struct device *dev;
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int nr_irqs;
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const struct dw_edma_plat_ops *ops;
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u32 flags;
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void __iomem *reg_base;
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u16 ll_wr_cnt;
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u16 ll_rd_cnt;
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/* link list address */
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struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
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struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
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/* data region */
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struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
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struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
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enum dw_edma_map_format mf;
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struct dw_edma *dw;
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};
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/* Export to the platform drivers */
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#if IS_REACHABLE(CONFIG_DW_EDMA)
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int dw_edma_probe(struct dw_edma_chip *chip);
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int dw_edma_remove(struct dw_edma_chip *chip);
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#else
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static inline int dw_edma_probe(struct dw_edma_chip *chip)
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{
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return -ENODEV;
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}
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static inline int dw_edma_remove(struct dw_edma_chip *chip)
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{
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return 0;
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}
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#endif /* CONFIG_DW_EDMA */
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#endif /* _DW_EDMA_H */
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