427 lines
13 KiB
C
427 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2019 ROHM Semiconductors */
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#ifndef __LINUX_MFD_BD71828_H__
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#define __LINUX_MFD_BD71828_H__
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#include <linux/mfd/rohm-generic.h>
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#include <linux/mfd/rohm-shared.h>
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/* Regulator IDs */
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enum {
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BD71828_BUCK1,
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BD71828_BUCK2,
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BD71828_BUCK3,
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BD71828_BUCK4,
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BD71828_BUCK5,
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BD71828_BUCK6,
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BD71828_BUCK7,
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BD71828_LDO1,
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BD71828_LDO2,
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BD71828_LDO3,
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BD71828_LDO4,
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BD71828_LDO5,
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BD71828_LDO6,
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BD71828_LDO_SNVS,
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BD71828_REGULATOR_AMOUNT,
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};
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#define BD71828_BUCK1267_VOLTS 0x100
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#define BD71828_BUCK3_VOLTS 0x20
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#define BD71828_BUCK4_VOLTS 0x40
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#define BD71828_BUCK5_VOLTS 0x20
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#define BD71828_LDO_VOLTS 0x40
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/* LDO6 is fixed 1.8V voltage */
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#define BD71828_LDO_6_VOLTAGE 1800000
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/* Registers and masks*/
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/* MODE control */
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#define BD71828_REG_PS_CTRL_1 0x04
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#define BD71828_REG_PS_CTRL_2 0x05
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#define BD71828_REG_PS_CTRL_3 0x06
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//#define BD71828_REG_SWRESET 0x06
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#define BD71828_MASK_RUN_LVL_CTRL 0x30
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/* Regulator control masks */
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#define BD71828_MASK_RAMP_DELAY 0x6
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#define BD71828_MASK_RUN_EN 0x08
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#define BD71828_MASK_SUSP_EN 0x04
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#define BD71828_MASK_IDLE_EN 0x02
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#define BD71828_MASK_LPSR_EN 0x01
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#define BD71828_MASK_RUN0_EN 0x01
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#define BD71828_MASK_RUN1_EN 0x02
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#define BD71828_MASK_RUN2_EN 0x04
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#define BD71828_MASK_RUN3_EN 0x08
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#define BD71828_MASK_DVS_BUCK1_CTRL 0x10
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#define BD71828_DVS_BUCK1_CTRL_I2C 0
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#define BD71828_DVS_BUCK1_USE_RUNLVL 0x10
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#define BD71828_MASK_DVS_BUCK2_CTRL 0x20
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#define BD71828_DVS_BUCK2_CTRL_I2C 0
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#define BD71828_DVS_BUCK2_USE_RUNLVL 0x20
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#define BD71828_MASK_DVS_BUCK6_CTRL 0x40
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#define BD71828_DVS_BUCK6_CTRL_I2C 0
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#define BD71828_DVS_BUCK6_USE_RUNLVL 0x40
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#define BD71828_MASK_DVS_BUCK7_CTRL 0x80
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#define BD71828_DVS_BUCK7_CTRL_I2C 0
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#define BD71828_DVS_BUCK7_USE_RUNLVL 0x80
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#define BD71828_MASK_BUCK1267_VOLT 0xff
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#define BD71828_MASK_BUCK3_VOLT 0x1f
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#define BD71828_MASK_BUCK4_VOLT 0x3f
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#define BD71828_MASK_BUCK5_VOLT 0x1f
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#define BD71828_MASK_LDO_VOLT 0x3f
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/* Regulator control regs */
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#define BD71828_REG_BUCK1_EN 0x08
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#define BD71828_REG_BUCK1_CTRL 0x09
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#define BD71828_REG_BUCK1_MODE 0x0a
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#define BD71828_REG_BUCK1_IDLE_VOLT 0x0b
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#define BD71828_REG_BUCK1_SUSP_VOLT 0x0c
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#define BD71828_REG_BUCK1_VOLT 0x0d
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#define BD71828_REG_BUCK2_EN 0x12
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#define BD71828_REG_BUCK2_CTRL 0x13
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#define BD71828_REG_BUCK2_MODE 0x14
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#define BD71828_REG_BUCK2_IDLE_VOLT 0x15
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#define BD71828_REG_BUCK2_SUSP_VOLT 0x16
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#define BD71828_REG_BUCK2_VOLT 0x17
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#define BD71828_REG_BUCK3_EN 0x1c
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#define BD71828_REG_BUCK3_MODE 0x1d
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#define BD71828_REG_BUCK3_VOLT 0x1e
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#define BD71828_REG_BUCK4_EN 0x1f
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#define BD71828_REG_BUCK4_MODE 0x20
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#define BD71828_REG_BUCK4_VOLT 0x21
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#define BD71828_REG_BUCK5_EN 0x22
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#define BD71828_REG_BUCK5_MODE 0x23
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#define BD71828_REG_BUCK5_VOLT 0x24
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#define BD71828_REG_BUCK6_EN 0x25
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#define BD71828_REG_BUCK6_CTRL 0x26
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#define BD71828_REG_BUCK6_MODE 0x27
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#define BD71828_REG_BUCK6_IDLE_VOLT 0x28
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#define BD71828_REG_BUCK6_SUSP_VOLT 0x29
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#define BD71828_REG_BUCK6_VOLT 0x2a
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#define BD71828_REG_BUCK7_EN 0x2f
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#define BD71828_REG_BUCK7_CTRL 0x30
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#define BD71828_REG_BUCK7_MODE 0x31
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#define BD71828_REG_BUCK7_IDLE_VOLT 0x32
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#define BD71828_REG_BUCK7_SUSP_VOLT 0x33
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#define BD71828_REG_BUCK7_VOLT 0x34
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#define BD71828_REG_LDO1_EN 0x39
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#define BD71828_REG_LDO1_VOLT 0x3a
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#define BD71828_REG_LDO2_EN 0x3b
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#define BD71828_REG_LDO2_VOLT 0x3c
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#define BD71828_REG_LDO3_EN 0x3d
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#define BD71828_REG_LDO3_VOLT 0x3e
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#define BD71828_REG_LDO4_EN 0x3f
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#define BD71828_REG_LDO4_VOLT 0x40
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#define BD71828_REG_LDO5_EN 0x41
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#define BD71828_REG_LDO5_VOLT 0x43
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#define BD71828_REG_LDO5_VOLT_OPT 0x42
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#define BD71828_REG_LDO6_EN 0x44
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//#define BD71828_REG_LDO6_VOLT 0x4
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#define BD71828_REG_LDO7_EN 0x45
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#define BD71828_REG_LDO7_VOLT 0x46
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/* GPIO */
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#define BD71828_GPIO_DRIVE_MASK 0x2
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#define BD71828_GPIO_OPEN_DRAIN 0x0
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#define BD71828_GPIO_PUSH_PULL 0x2
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#define BD71828_GPIO_OUT_HI 0x1
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#define BD71828_GPIO_OUT_LO 0x0
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#define BD71828_GPIO_OUT_MASK 0x1
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#define BD71828_REG_GPIO_CTRL1 0x47
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#define BD71828_REG_GPIO_CTRL2 0x48
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#define BD71828_REG_GPIO_CTRL3 0x49
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#define BD71828_REG_IO_STAT 0xed
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/* clk */
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#define BD71828_REG_OUT32K 0x4b
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/* RTC */
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#define BD71828_REG_RTC_SEC 0x4c
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#define BD71828_REG_RTC_MINUTE 0x4d
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#define BD71828_REG_RTC_HOUR 0x4e
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#define BD71828_REG_RTC_WEEK 0x4f
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#define BD71828_REG_RTC_DAY 0x50
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#define BD71828_REG_RTC_MONTH 0x51
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#define BD71828_REG_RTC_YEAR 0x52
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#define BD71828_REG_RTC_ALM0_SEC 0x53
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#define BD71828_REG_RTC_ALM_START BD71828_REG_RTC_ALM0_SEC
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#define BD71828_REG_RTC_ALM0_MINUTE 0x54
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#define BD71828_REG_RTC_ALM0_HOUR 0x55
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#define BD71828_REG_RTC_ALM0_WEEK 0x56
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#define BD71828_REG_RTC_ALM0_DAY 0x57
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#define BD71828_REG_RTC_ALM0_MONTH 0x58
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#define BD71828_REG_RTC_ALM0_YEAR 0x59
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#define BD71828_REG_RTC_ALM0_MASK 0x61
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#define BD71828_REG_RTC_ALM1_SEC 0x5a
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#define BD71828_REG_RTC_ALM1_MINUTE 0x5b
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#define BD71828_REG_RTC_ALM1_HOUR 0x5c
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#define BD71828_REG_RTC_ALM1_WEEK 0x5d
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#define BD71828_REG_RTC_ALM1_DAY 0x5e
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#define BD71828_REG_RTC_ALM1_MONTH 0x5f
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#define BD71828_REG_RTC_ALM1_YEAR 0x60
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#define BD71828_REG_RTC_ALM1_MASK 0x62
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#define BD71828_REG_RTC_ALM2 0x63
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#define BD71828_REG_RTC_START BD71828_REG_RTC_SEC
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/* Charger/Battey */
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#define BD71828_REG_CHG_STATE 0x65
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#define BD71828_REG_CHG_FULL 0xd2
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/* LEDs */
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#define BD71828_REG_LED_CTRL 0x4A
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#define BD71828_MASK_LED_AMBER 0x80
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#define BD71828_MASK_LED_GREEN 0x40
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#define BD71828_LED_ON 0xff
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#define BD71828_LED_OFF 0x0
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/* IRQ registers */
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#define BD71828_REG_INT_MASK_BUCK 0xd3
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#define BD71828_REG_INT_MASK_DCIN1 0xd4
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#define BD71828_REG_INT_MASK_DCIN2 0xd5
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#define BD71828_REG_INT_MASK_VSYS 0xd6
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#define BD71828_REG_INT_MASK_CHG 0xd7
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#define BD71828_REG_INT_MASK_BAT 0xd8
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#define BD71828_REG_INT_MASK_BAT_MON1 0xd9
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#define BD71828_REG_INT_MASK_BAT_MON2 0xda
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#define BD71828_REG_INT_MASK_BAT_MON3 0xdb
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#define BD71828_REG_INT_MASK_BAT_MON4 0xdc
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#define BD71828_REG_INT_MASK_TEMP 0xdd
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#define BD71828_REG_INT_MASK_RTC 0xde
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#define BD71828_REG_INT_MAIN 0xdf
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#define BD71828_REG_INT_BUCK 0xe0
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#define BD71828_REG_INT_DCIN1 0xe1
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#define BD71828_REG_INT_DCIN2 0xe2
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#define BD71828_REG_INT_VSYS 0xe3
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#define BD71828_REG_INT_CHG 0xe4
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#define BD71828_REG_INT_BAT 0xe5
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#define BD71828_REG_INT_BAT_MON1 0xe6
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#define BD71828_REG_INT_BAT_MON2 0xe7
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#define BD71828_REG_INT_BAT_MON3 0xe8
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#define BD71828_REG_INT_BAT_MON4 0xe9
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#define BD71828_REG_INT_TEMP 0xea
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#define BD71828_REG_INT_RTC 0xeb
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#define BD71828_REG_INT_UPDATE 0xec
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#define BD71828_MAX_REGISTER BD71828_REG_IO_STAT
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/* Masks for main IRQ register bits */
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enum {
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BD71828_INT_BUCK,
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#define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK)
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BD71828_INT_DCIN,
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#define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN)
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BD71828_INT_VSYS,
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#define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS)
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BD71828_INT_CHG,
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#define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG)
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BD71828_INT_BAT,
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#define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT)
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BD71828_INT_BAT_MON,
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#define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON)
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BD71828_INT_TEMP,
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#define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP)
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BD71828_INT_RTC,
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#define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC)
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};
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/* Interrupts */
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enum {
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/* BUCK reg interrupts */
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BD71828_INT_BUCK1_OCP,
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BD71828_INT_BUCK2_OCP,
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BD71828_INT_BUCK3_OCP,
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BD71828_INT_BUCK4_OCP,
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BD71828_INT_BUCK5_OCP,
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BD71828_INT_BUCK6_OCP,
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BD71828_INT_BUCK7_OCP,
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BD71828_INT_PGFAULT,
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/* DCIN1 interrupts */
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BD71828_INT_DCIN_DET,
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BD71828_INT_DCIN_RMV,
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BD71828_INT_CLPS_OUT,
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BD71828_INT_CLPS_IN,
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/* DCIN2 interrupts */
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BD71828_INT_DCIN_MON_RES,
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BD71828_INT_DCIN_MON_DET,
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BD71828_INT_LONGPUSH,
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BD71828_INT_MIDPUSH,
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BD71828_INT_SHORTPUSH,
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BD71828_INT_PUSH,
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BD71828_INT_WDOG,
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BD71828_INT_SWRESET,
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/* Vsys */
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BD71828_INT_VSYS_UV_RES,
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BD71828_INT_VSYS_UV_DET,
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BD71828_INT_VSYS_LOW_RES,
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BD71828_INT_VSYS_LOW_DET,
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BD71828_INT_VSYS_HALL_IN,
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BD71828_INT_VSYS_HALL_TOGGLE,
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BD71828_INT_VSYS_MON_RES,
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BD71828_INT_VSYS_MON_DET,
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/* Charger */
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BD71828_INT_CHG_DCIN_ILIM,
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BD71828_INT_CHG_TOPOFF_TO_DONE,
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BD71828_INT_CHG_WDG_TEMP,
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BD71828_INT_CHG_WDG_TIME,
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BD71828_INT_CHG_RECHARGE_RES,
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BD71828_INT_CHG_RECHARGE_DET,
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BD71828_INT_CHG_RANGED_TEMP_TRANSITION,
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BD71828_INT_CHG_STATE_TRANSITION,
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/* Battery */
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BD71828_INT_BAT_TEMP_NORMAL,
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BD71828_INT_BAT_TEMP_ERANGE,
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BD71828_INT_BAT_TEMP_WARN,
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BD71828_INT_BAT_REMOVED,
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BD71828_INT_BAT_DETECTED,
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BD71828_INT_THERM_REMOVED,
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BD71828_INT_THERM_DETECTED,
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/* Battery Mon 1 */
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BD71828_INT_BAT_DEAD,
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BD71828_INT_BAT_SHORTC_RES,
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BD71828_INT_BAT_SHORTC_DET,
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BD71828_INT_BAT_LOW_VOLT_RES,
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BD71828_INT_BAT_LOW_VOLT_DET,
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BD71828_INT_BAT_OVER_VOLT_RES,
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BD71828_INT_BAT_OVER_VOLT_DET,
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/* Battery Mon 2 */
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BD71828_INT_BAT_MON_RES,
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BD71828_INT_BAT_MON_DET,
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/* Battery Mon 3 (Coulomb counter) */
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BD71828_INT_BAT_CC_MON1,
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BD71828_INT_BAT_CC_MON2,
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BD71828_INT_BAT_CC_MON3,
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/* Battery Mon 4 */
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BD71828_INT_BAT_OVER_CURR_1_RES,
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BD71828_INT_BAT_OVER_CURR_1_DET,
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BD71828_INT_BAT_OVER_CURR_2_RES,
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BD71828_INT_BAT_OVER_CURR_2_DET,
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BD71828_INT_BAT_OVER_CURR_3_RES,
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BD71828_INT_BAT_OVER_CURR_3_DET,
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/* Temperature */
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BD71828_INT_TEMP_BAT_LOW_RES,
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BD71828_INT_TEMP_BAT_LOW_DET,
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BD71828_INT_TEMP_BAT_HI_RES,
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BD71828_INT_TEMP_BAT_HI_DET,
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BD71828_INT_TEMP_CHIP_OVER_125_RES,
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BD71828_INT_TEMP_CHIP_OVER_125_DET,
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BD71828_INT_TEMP_CHIP_OVER_VF_DET,
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BD71828_INT_TEMP_CHIP_OVER_VF_RES,
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/* RTC Alarm */
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BD71828_INT_RTC0,
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BD71828_INT_RTC1,
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BD71828_INT_RTC2,
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};
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#define BD71828_INT_BUCK1_OCP_MASK 0x1
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#define BD71828_INT_BUCK2_OCP_MASK 0x2
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#define BD71828_INT_BUCK3_OCP_MASK 0x4
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#define BD71828_INT_BUCK4_OCP_MASK 0x8
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#define BD71828_INT_BUCK5_OCP_MASK 0x10
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#define BD71828_INT_BUCK6_OCP_MASK 0x20
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#define BD71828_INT_BUCK7_OCP_MASK 0x40
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#define BD71828_INT_PGFAULT_MASK 0x80
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#define BD71828_INT_DCIN_DET_MASK 0x1
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#define BD71828_INT_DCIN_RMV_MASK 0x2
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#define BD71828_INT_CLPS_OUT_MASK 0x4
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#define BD71828_INT_CLPS_IN_MASK 0x8
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/* DCIN2 interrupts */
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#define BD71828_INT_DCIN_MON_RES_MASK 0x1
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#define BD71828_INT_DCIN_MON_DET_MASK 0x2
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#define BD71828_INT_LONGPUSH_MASK 0x4
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#define BD71828_INT_MIDPUSH_MASK 0x8
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#define BD71828_INT_SHORTPUSH_MASK 0x10
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#define BD71828_INT_PUSH_MASK 0x20
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#define BD71828_INT_WDOG_MASK 0x40
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#define BD71828_INT_SWRESET_MASK 0x80
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/* Vsys */
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#define BD71828_INT_VSYS_UV_RES_MASK 0x1
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#define BD71828_INT_VSYS_UV_DET_MASK 0x2
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#define BD71828_INT_VSYS_LOW_RES_MASK 0x4
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#define BD71828_INT_VSYS_LOW_DET_MASK 0x8
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#define BD71828_INT_VSYS_HALL_IN_MASK 0x10
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#define BD71828_INT_VSYS_HALL_TOGGLE_MASK 0x20
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#define BD71828_INT_VSYS_MON_RES_MASK 0x40
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#define BD71828_INT_VSYS_MON_DET_MASK 0x80
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/* Charger */
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#define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1
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#define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK 0x2
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#define BD71828_INT_CHG_WDG_TEMP_MASK 0x4
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#define BD71828_INT_CHG_WDG_TIME_MASK 0x8
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#define BD71828_INT_CHG_RECHARGE_RES_MASK 0x10
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#define BD71828_INT_CHG_RECHARGE_DET_MASK 0x20
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#define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40
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#define BD71828_INT_CHG_STATE_TRANSITION_MASK 0x80
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/* Battery */
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#define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1
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#define BD71828_INT_BAT_TEMP_ERANGE_MASK 0x2
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#define BD71828_INT_BAT_TEMP_WARN_MASK 0x4
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#define BD71828_INT_BAT_REMOVED_MASK 0x10
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#define BD71828_INT_BAT_DETECTED_MASK 0x20
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#define BD71828_INT_THERM_REMOVED_MASK 0x40
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#define BD71828_INT_THERM_DETECTED_MASK 0x80
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/* Battery Mon 1 */
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#define BD71828_INT_BAT_DEAD_MASK 0x2
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#define BD71828_INT_BAT_SHORTC_RES_MASK 0x4
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#define BD71828_INT_BAT_SHORTC_DET_MASK 0x8
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#define BD71828_INT_BAT_LOW_VOLT_RES_MASK 0x10
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#define BD71828_INT_BAT_LOW_VOLT_DET_MASK 0x20
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#define BD71828_INT_BAT_OVER_VOLT_RES_MASK 0x40
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#define BD71828_INT_BAT_OVER_VOLT_DET_MASK 0x80
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/* Battery Mon 2 */
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#define BD71828_INT_BAT_MON_RES_MASK 0x1
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#define BD71828_INT_BAT_MON_DET_MASK 0x2
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/* Battery Mon 3 (Coulomb counter) */
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#define BD71828_INT_BAT_CC_MON1_MASK 0x1
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#define BD71828_INT_BAT_CC_MON2_MASK 0x2
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#define BD71828_INT_BAT_CC_MON3_MASK 0x4
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/* Battery Mon 4 */
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#define BD71828_INT_BAT_OVER_CURR_1_RES_MASK 0x1
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#define BD71828_INT_BAT_OVER_CURR_1_DET_MASK 0x2
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#define BD71828_INT_BAT_OVER_CURR_2_RES_MASK 0x4
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#define BD71828_INT_BAT_OVER_CURR_2_DET_MASK 0x8
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#define BD71828_INT_BAT_OVER_CURR_3_RES_MASK 0x10
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#define BD71828_INT_BAT_OVER_CURR_3_DET_MASK 0x20
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/* Temperature */
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#define BD71828_INT_TEMP_BAT_LOW_RES_MASK 0x1
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#define BD71828_INT_TEMP_BAT_LOW_DET_MASK 0x2
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#define BD71828_INT_TEMP_BAT_HI_RES_MASK 0x4
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#define BD71828_INT_TEMP_BAT_HI_DET_MASK 0x8
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#define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK 0x10
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#define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK 0x20
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#define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK 0x40
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#define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK 0x80
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/* RTC Alarm */
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#define BD71828_INT_RTC0_MASK 0x1
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#define BD71828_INT_RTC1_MASK 0x2
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#define BD71828_INT_RTC2_MASK 0x4
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#define BD71828_OUT_TYPE_MASK 0x2
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#define BD71828_OUT_TYPE_OPEN_DRAIN 0x0
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#define BD71828_OUT_TYPE_CMOS 0x2
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#endif /* __LINUX_MFD_BD71828_H__ */
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