1334 lines
35 KiB
C
1334 lines
35 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_DRIVER_H
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#define MLX5_DRIVER_H
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#include <linux/kernel.h>
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#include <linux/completion.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/spinlock_types.h>
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#include <linux/semaphore.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/xarray.h>
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#include <linux/workqueue.h>
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#include <linux/mempool.h>
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#include <linux/interrupt.h>
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#include <linux/idr.h>
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#include <linux/notifier.h>
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#include <linux/refcount.h>
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#include <linux/auxiliary_bus.h>
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#include <linux/mutex.h>
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/doorbell.h>
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#include <linux/mlx5/eq.h>
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#include <linux/timecounter.h>
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#include <linux/ptp_clock_kernel.h>
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#include <net/devlink.h>
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#define MLX5_ADEV_NAME "mlx5_core"
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#define MLX5_IRQ_EQ_CTRL (U8_MAX)
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enum {
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MLX5_BOARD_ID_LEN = 64,
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};
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enum {
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MLX5_CMD_WQ_MAX_NAME = 32,
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};
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enum {
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CMD_OWNER_SW = 0x0,
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CMD_OWNER_HW = 0x1,
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CMD_STATUS_SUCCESS = 0,
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};
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enum mlx5_sqp_t {
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MLX5_SQP_SMI = 0,
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MLX5_SQP_GSI = 1,
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MLX5_SQP_IEEE_1588 = 2,
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MLX5_SQP_SNIFFER = 3,
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MLX5_SQP_SYNC_UMR = 4,
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};
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enum {
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MLX5_MAX_PORTS = 4,
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};
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enum {
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MLX5_ATOMIC_MODE_OFFSET = 16,
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MLX5_ATOMIC_MODE_IB_COMP = 1,
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MLX5_ATOMIC_MODE_CX = 2,
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MLX5_ATOMIC_MODE_8B = 3,
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MLX5_ATOMIC_MODE_16B = 4,
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MLX5_ATOMIC_MODE_32B = 5,
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MLX5_ATOMIC_MODE_64B = 6,
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MLX5_ATOMIC_MODE_128B = 7,
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MLX5_ATOMIC_MODE_256B = 8,
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};
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enum {
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MLX5_REG_SBPR = 0xb001,
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MLX5_REG_SBCM = 0xb002,
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MLX5_REG_QPTS = 0x4002,
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MLX5_REG_QETCR = 0x4005,
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MLX5_REG_QTCT = 0x400a,
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MLX5_REG_QPDPM = 0x4013,
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MLX5_REG_QCAM = 0x4019,
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MLX5_REG_DCBX_PARAM = 0x4020,
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MLX5_REG_DCBX_APP = 0x4021,
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MLX5_REG_FPGA_CAP = 0x4022,
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MLX5_REG_FPGA_CTRL = 0x4023,
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MLX5_REG_FPGA_ACCESS_REG = 0x4024,
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MLX5_REG_CORE_DUMP = 0x402e,
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MLX5_REG_PCAP = 0x5001,
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MLX5_REG_PMTU = 0x5003,
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MLX5_REG_PTYS = 0x5004,
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MLX5_REG_PAOS = 0x5006,
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MLX5_REG_PFCC = 0x5007,
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MLX5_REG_PPCNT = 0x5008,
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MLX5_REG_PPTB = 0x500b,
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MLX5_REG_PBMC = 0x500c,
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MLX5_REG_PMAOS = 0x5012,
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MLX5_REG_PUDE = 0x5009,
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MLX5_REG_PMPE = 0x5010,
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MLX5_REG_PELC = 0x500e,
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MLX5_REG_PVLC = 0x500f,
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MLX5_REG_PCMR = 0x5041,
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MLX5_REG_PDDR = 0x5031,
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MLX5_REG_PMLP = 0x5002,
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MLX5_REG_PPLM = 0x5023,
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MLX5_REG_PCAM = 0x507f,
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MLX5_REG_NODE_DESC = 0x6001,
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MLX5_REG_HOST_ENDIANNESS = 0x7004,
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MLX5_REG_MTMP = 0x900A,
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MLX5_REG_MCIA = 0x9014,
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MLX5_REG_MFRL = 0x9028,
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MLX5_REG_MLCR = 0x902b,
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MLX5_REG_MRTC = 0x902d,
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MLX5_REG_MTRC_CAP = 0x9040,
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MLX5_REG_MTRC_CONF = 0x9041,
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MLX5_REG_MTRC_STDB = 0x9042,
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MLX5_REG_MTRC_CTRL = 0x9043,
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MLX5_REG_MPEIN = 0x9050,
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MLX5_REG_MPCNT = 0x9051,
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MLX5_REG_MTPPS = 0x9053,
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MLX5_REG_MTPPSE = 0x9054,
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MLX5_REG_MTUTC = 0x9055,
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MLX5_REG_MPEGC = 0x9056,
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MLX5_REG_MCQS = 0x9060,
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MLX5_REG_MCQI = 0x9061,
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MLX5_REG_MCC = 0x9062,
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MLX5_REG_MCDA = 0x9063,
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MLX5_REG_MCAM = 0x907f,
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MLX5_REG_MIRC = 0x9162,
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MLX5_REG_SBCAM = 0xB01F,
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MLX5_REG_RESOURCE_DUMP = 0xC000,
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MLX5_REG_DTOR = 0xC00E,
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};
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enum mlx5_qpts_trust_state {
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MLX5_QPTS_TRUST_PCP = 1,
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MLX5_QPTS_TRUST_DSCP = 2,
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};
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enum mlx5_dcbx_oper_mode {
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MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
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MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
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};
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enum {
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MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
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MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
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MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
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MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
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};
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enum mlx5_page_fault_resume_flags {
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MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
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MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
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MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
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MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
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};
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enum dbg_rsc_type {
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MLX5_DBG_RSC_QP,
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MLX5_DBG_RSC_EQ,
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MLX5_DBG_RSC_CQ,
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};
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enum port_state_policy {
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MLX5_POLICY_DOWN = 0,
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MLX5_POLICY_UP = 1,
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MLX5_POLICY_FOLLOW = 2,
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MLX5_POLICY_INVALID = 0xffffffff
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};
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enum mlx5_coredev_type {
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MLX5_COREDEV_PF,
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MLX5_COREDEV_VF,
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MLX5_COREDEV_SF,
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};
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struct mlx5_field_desc {
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int i;
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};
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struct mlx5_rsc_debug {
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struct mlx5_core_dev *dev;
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void *object;
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enum dbg_rsc_type type;
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struct dentry *root;
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struct mlx5_field_desc fields[];
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};
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enum mlx5_dev_event {
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MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
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MLX5_DEV_EVENT_PORT_AFFINITY = 129,
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MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
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};
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enum mlx5_port_status {
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MLX5_PORT_UP = 1,
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MLX5_PORT_DOWN = 2,
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};
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enum mlx5_cmdif_state {
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MLX5_CMDIF_STATE_UNINITIALIZED,
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MLX5_CMDIF_STATE_UP,
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MLX5_CMDIF_STATE_DOWN,
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};
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struct mlx5_cmd_first {
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__be32 data[4];
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};
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struct mlx5_cmd_msg {
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struct list_head list;
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struct cmd_msg_cache *parent;
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u32 len;
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struct mlx5_cmd_first first;
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struct mlx5_cmd_mailbox *next;
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};
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struct mlx5_cmd_debug {
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struct dentry *dbg_root;
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void *in_msg;
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void *out_msg;
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u8 status;
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u16 inlen;
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u16 outlen;
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};
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struct cmd_msg_cache {
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/* protect block chain allocations
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*/
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spinlock_t lock;
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struct list_head head;
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unsigned int max_inbox_size;
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unsigned int num_ent;
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};
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enum {
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MLX5_NUM_COMMAND_CACHES = 5,
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};
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struct mlx5_cmd_stats {
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u64 sum;
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u64 n;
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/* number of times command failed */
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u64 failed;
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/* number of times command failed on bad status returned by FW */
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u64 failed_mbox_status;
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/* last command failed returned errno */
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u32 last_failed_errno;
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/* last bad status returned by FW */
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u8 last_failed_mbox_status;
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/* last command failed syndrome returned by FW */
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u32 last_failed_syndrome;
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struct dentry *root;
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/* protect command average calculations */
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spinlock_t lock;
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};
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struct mlx5_cmd {
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struct mlx5_nb nb;
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enum mlx5_cmdif_state state;
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void *cmd_alloc_buf;
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dma_addr_t alloc_dma;
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int alloc_size;
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void *cmd_buf;
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dma_addr_t dma;
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u16 cmdif_rev;
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u8 log_sz;
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u8 log_stride;
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int max_reg_cmds;
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int events;
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u32 __iomem *vector;
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/* protect command queue allocations
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*/
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spinlock_t alloc_lock;
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/* protect token allocations
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*/
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spinlock_t token_lock;
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u8 token;
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unsigned long bitmask;
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char wq_name[MLX5_CMD_WQ_MAX_NAME];
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struct workqueue_struct *wq;
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struct semaphore sem;
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struct semaphore pages_sem;
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struct semaphore throttle_sem;
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int mode;
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u16 allowed_opcode;
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struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
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struct dma_pool *pool;
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struct mlx5_cmd_debug dbg;
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struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
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int checksum_disabled;
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struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
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};
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struct mlx5_cmd_mailbox {
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void *buf;
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dma_addr_t dma;
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struct mlx5_cmd_mailbox *next;
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};
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struct mlx5_buf_list {
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void *buf;
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dma_addr_t map;
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};
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struct mlx5_frag_buf {
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struct mlx5_buf_list *frags;
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int npages;
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int size;
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u8 page_shift;
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};
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struct mlx5_frag_buf_ctrl {
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struct mlx5_buf_list *frags;
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u32 sz_m1;
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u16 frag_sz_m1;
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u16 strides_offset;
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u8 log_sz;
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u8 log_stride;
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u8 log_frag_strides;
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};
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struct mlx5_core_psv {
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u32 psv_idx;
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struct psv_layout {
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u32 pd;
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u16 syndrome;
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u16 reserved;
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u16 bg;
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u16 app_tag;
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u32 ref_tag;
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} psv;
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};
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struct mlx5_core_sig_ctx {
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struct mlx5_core_psv psv_memory;
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struct mlx5_core_psv psv_wire;
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struct ib_sig_err err_item;
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bool sig_status_checked;
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bool sig_err_exists;
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u32 sigerr_count;
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};
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#define MLX5_24BIT_MASK ((1 << 24) - 1)
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enum mlx5_res_type {
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MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
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MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
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MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
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MLX5_RES_SRQ = 3,
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MLX5_RES_XSRQ = 4,
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MLX5_RES_XRQ = 5,
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};
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struct mlx5_core_rsc_common {
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enum mlx5_res_type res;
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refcount_t refcount;
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struct completion free;
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};
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struct mlx5_uars_page {
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void __iomem *map;
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bool wc;
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u32 index;
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struct list_head list;
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unsigned int bfregs;
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unsigned long *reg_bitmap; /* for non fast path bf regs */
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unsigned long *fp_bitmap;
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unsigned int reg_avail;
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unsigned int fp_avail;
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struct kref ref_count;
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struct mlx5_core_dev *mdev;
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};
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struct mlx5_bfreg_head {
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/* protect blue flame registers allocations */
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struct mutex lock;
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struct list_head list;
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};
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struct mlx5_bfreg_data {
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struct mlx5_bfreg_head reg_head;
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struct mlx5_bfreg_head wc_head;
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};
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struct mlx5_sq_bfreg {
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void __iomem *map;
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struct mlx5_uars_page *up;
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bool wc;
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u32 index;
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unsigned int offset;
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};
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struct mlx5_core_health {
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struct health_buffer __iomem *health;
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__be32 __iomem *health_counter;
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struct timer_list timer;
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u32 prev;
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int miss_counter;
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u8 synd;
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u32 fatal_error;
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u32 crdump_size;
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struct workqueue_struct *wq;
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unsigned long flags;
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struct work_struct fatal_report_work;
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struct work_struct report_work;
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struct devlink_health_reporter *fw_reporter;
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struct devlink_health_reporter *fw_fatal_reporter;
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struct devlink_health_reporter *vnic_reporter;
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struct delayed_work update_fw_log_ts_work;
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};
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enum {
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MLX5_PF_NOTIFY_DISABLE_VF,
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MLX5_PF_NOTIFY_ENABLE_VF,
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};
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struct mlx5_vf_context {
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int enabled;
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u64 port_guid;
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u64 node_guid;
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/* Valid bits are used to validate administrative guid only.
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* Enabled after ndo_set_vf_guid
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*/
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u8 port_guid_valid:1;
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u8 node_guid_valid:1;
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enum port_state_policy policy;
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struct blocking_notifier_head notifier;
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};
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struct mlx5_core_sriov {
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struct mlx5_vf_context *vfs_ctx;
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int num_vfs;
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u16 max_vfs;
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u16 max_ec_vfs;
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};
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struct mlx5_fc_pool {
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struct mlx5_core_dev *dev;
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struct mutex pool_lock; /* protects pool lists */
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struct list_head fully_used;
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struct list_head partially_used;
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struct list_head unused;
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int available_fcs;
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int used_fcs;
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int threshold;
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};
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struct mlx5_fc_stats {
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spinlock_t counters_idr_lock; /* protects counters_idr */
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struct idr counters_idr;
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struct list_head counters;
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struct llist_head addlist;
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struct llist_head dellist;
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struct workqueue_struct *wq;
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struct delayed_work work;
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unsigned long next_query;
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unsigned long sampling_interval; /* jiffies */
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u32 *bulk_query_out;
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int bulk_query_len;
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size_t num_counters;
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bool bulk_query_alloc_failed;
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unsigned long next_bulk_query_alloc;
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struct mlx5_fc_pool fc_pool;
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};
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struct mlx5_events;
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struct mlx5_mpfs;
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struct mlx5_eswitch;
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struct mlx5_lag;
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struct mlx5_devcom;
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struct mlx5_fw_reset;
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struct mlx5_eq_table;
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struct mlx5_irq_table;
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struct mlx5_vhca_state_notifier;
|
|
struct mlx5_sf_dev_table;
|
|
struct mlx5_sf_hw_table;
|
|
struct mlx5_sf_table;
|
|
struct mlx5_crypto_dek_priv;
|
|
|
|
struct mlx5_rate_limit {
|
|
u32 rate;
|
|
u32 max_burst_sz;
|
|
u16 typical_pkt_sz;
|
|
};
|
|
|
|
struct mlx5_rl_entry {
|
|
u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
|
|
u64 refcount;
|
|
u16 index;
|
|
u16 uid;
|
|
u8 dedicated : 1;
|
|
};
|
|
|
|
struct mlx5_rl_table {
|
|
/* protect rate limit table */
|
|
struct mutex rl_lock;
|
|
u16 max_size;
|
|
u32 max_rate;
|
|
u32 min_rate;
|
|
struct mlx5_rl_entry *rl_entry;
|
|
u64 refcount;
|
|
};
|
|
|
|
struct mlx5_core_roce {
|
|
struct mlx5_flow_table *ft;
|
|
struct mlx5_flow_group *fg;
|
|
struct mlx5_flow_handle *allow_rule;
|
|
};
|
|
|
|
enum {
|
|
MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
|
|
MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
|
|
/* Set during device detach to block any further devices
|
|
* creation/deletion on drivers rescan. Unset during device attach.
|
|
*/
|
|
MLX5_PRIV_FLAGS_DETACH = 1 << 2,
|
|
};
|
|
|
|
struct mlx5_adev {
|
|
struct auxiliary_device adev;
|
|
struct mlx5_core_dev *mdev;
|
|
int idx;
|
|
};
|
|
|
|
struct mlx5_debugfs_entries {
|
|
struct dentry *dbg_root;
|
|
struct dentry *qp_debugfs;
|
|
struct dentry *eq_debugfs;
|
|
struct dentry *cq_debugfs;
|
|
struct dentry *cmdif_debugfs;
|
|
struct dentry *pages_debugfs;
|
|
struct dentry *lag_debugfs;
|
|
};
|
|
|
|
enum mlx5_func_type {
|
|
MLX5_PF,
|
|
MLX5_VF,
|
|
MLX5_SF,
|
|
MLX5_HOST_PF,
|
|
MLX5_EC_VF,
|
|
MLX5_FUNC_TYPE_NUM,
|
|
};
|
|
|
|
struct mlx5_ft_pool;
|
|
struct mlx5_priv {
|
|
/* IRQ table valid only for real pci devices PF or VF */
|
|
struct mlx5_irq_table *irq_table;
|
|
struct mlx5_eq_table *eq_table;
|
|
|
|
/* pages stuff */
|
|
struct mlx5_nb pg_nb;
|
|
struct workqueue_struct *pg_wq;
|
|
struct xarray page_root_xa;
|
|
atomic_t reg_pages;
|
|
struct list_head free_list;
|
|
u32 fw_pages;
|
|
u32 page_counters[MLX5_FUNC_TYPE_NUM];
|
|
u32 fw_pages_alloc_failed;
|
|
u32 give_pages_dropped;
|
|
u32 reclaim_pages_discard;
|
|
|
|
struct mlx5_core_health health;
|
|
struct list_head traps;
|
|
|
|
struct mlx5_debugfs_entries dbg;
|
|
|
|
/* start: alloc staff */
|
|
/* protect buffer allocation according to numa node */
|
|
struct mutex alloc_mutex;
|
|
int numa_node;
|
|
|
|
struct mutex pgdir_mutex;
|
|
struct list_head pgdir_list;
|
|
/* end: alloc staff */
|
|
|
|
struct mlx5_adev **adev;
|
|
int adev_idx;
|
|
int sw_vhca_id;
|
|
struct mlx5_events *events;
|
|
|
|
struct mlx5_flow_steering *steering;
|
|
struct mlx5_mpfs *mpfs;
|
|
struct mlx5_eswitch *eswitch;
|
|
struct mlx5_core_sriov sriov;
|
|
struct mlx5_lag *lag;
|
|
u32 flags;
|
|
struct mlx5_devcom *devcom;
|
|
struct mlx5_fw_reset *fw_reset;
|
|
struct mlx5_core_roce roce;
|
|
struct mlx5_fc_stats fc_stats;
|
|
struct mlx5_rl_table rl_table;
|
|
struct mlx5_ft_pool *ft_pool;
|
|
|
|
struct mlx5_bfreg_data bfregs;
|
|
struct mlx5_uars_page *uar;
|
|
#ifdef CONFIG_MLX5_SF
|
|
struct mlx5_vhca_state_notifier *vhca_state_notifier;
|
|
struct mlx5_sf_dev_table *sf_dev_table;
|
|
struct mlx5_core_dev *parent_mdev;
|
|
#endif
|
|
#ifdef CONFIG_MLX5_SF_MANAGER
|
|
struct mlx5_sf_hw_table *sf_hw_table;
|
|
struct mlx5_sf_table *sf_table;
|
|
#endif
|
|
};
|
|
|
|
enum mlx5_device_state {
|
|
MLX5_DEVICE_STATE_UP = 1,
|
|
MLX5_DEVICE_STATE_INTERNAL_ERROR,
|
|
};
|
|
|
|
enum mlx5_interface_state {
|
|
MLX5_INTERFACE_STATE_UP = BIT(0),
|
|
MLX5_BREAK_FW_WAIT = BIT(1),
|
|
};
|
|
|
|
enum mlx5_pci_status {
|
|
MLX5_PCI_STATUS_DISABLED,
|
|
MLX5_PCI_STATUS_ENABLED,
|
|
};
|
|
|
|
enum mlx5_pagefault_type_flags {
|
|
MLX5_PFAULT_REQUESTOR = 1 << 0,
|
|
MLX5_PFAULT_WRITE = 1 << 1,
|
|
MLX5_PFAULT_RDMA = 1 << 2,
|
|
};
|
|
|
|
struct mlx5_td {
|
|
/* protects tirs list changes while tirs refresh */
|
|
struct mutex list_lock;
|
|
struct list_head tirs_list;
|
|
u32 tdn;
|
|
};
|
|
|
|
struct mlx5e_resources {
|
|
struct mlx5e_hw_objs {
|
|
u32 pdn;
|
|
struct mlx5_td td;
|
|
u32 mkey;
|
|
struct mlx5_sq_bfreg bfreg;
|
|
} hw_objs;
|
|
struct net_device *uplink_netdev;
|
|
struct mutex uplink_netdev_lock;
|
|
struct mlx5_crypto_dek_priv *dek_priv;
|
|
};
|
|
|
|
enum mlx5_sw_icm_type {
|
|
MLX5_SW_ICM_TYPE_STEERING,
|
|
MLX5_SW_ICM_TYPE_HEADER_MODIFY,
|
|
MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
|
|
};
|
|
|
|
#define MLX5_MAX_RESERVED_GIDS 8
|
|
|
|
struct mlx5_rsvd_gids {
|
|
unsigned int start;
|
|
unsigned int count;
|
|
struct ida ida;
|
|
};
|
|
|
|
#define MAX_PIN_NUM 8
|
|
struct mlx5_pps {
|
|
u8 pin_caps[MAX_PIN_NUM];
|
|
struct work_struct out_work;
|
|
u64 start[MAX_PIN_NUM];
|
|
u8 enabled;
|
|
u64 min_npps_period;
|
|
u64 min_out_pulse_duration_ns;
|
|
};
|
|
|
|
struct mlx5_timer {
|
|
struct cyclecounter cycles;
|
|
struct timecounter tc;
|
|
u32 nominal_c_mult;
|
|
unsigned long overflow_period;
|
|
struct delayed_work overflow_work;
|
|
};
|
|
|
|
struct mlx5_clock {
|
|
struct mlx5_nb pps_nb;
|
|
seqlock_t lock;
|
|
struct hwtstamp_config hwtstamp_config;
|
|
struct ptp_clock *ptp;
|
|
struct ptp_clock_info ptp_info;
|
|
struct mlx5_pps pps_info;
|
|
struct mlx5_timer timer;
|
|
};
|
|
|
|
struct mlx5_dm;
|
|
struct mlx5_fw_tracer;
|
|
struct mlx5_vxlan;
|
|
struct mlx5_geneve;
|
|
struct mlx5_hv_vhca;
|
|
struct mlx5_thermal;
|
|
|
|
#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
|
|
#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
|
|
|
|
enum {
|
|
MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
|
|
MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
|
|
};
|
|
|
|
enum {
|
|
MKEY_CACHE_LAST_STD_ENTRY = 20,
|
|
MLX5_IMR_KSM_CACHE_ENTRY,
|
|
MAX_MKEY_CACHE_ENTRIES
|
|
};
|
|
|
|
struct mlx5_profile {
|
|
u64 mask;
|
|
u8 log_max_qp;
|
|
u8 num_cmd_caches;
|
|
struct {
|
|
int size;
|
|
int limit;
|
|
} mr_cache[MAX_MKEY_CACHE_ENTRIES];
|
|
};
|
|
|
|
struct mlx5_hca_cap {
|
|
u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
|
|
u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
|
|
};
|
|
|
|
struct mlx5_core_dev {
|
|
struct device *device;
|
|
enum mlx5_coredev_type coredev_type;
|
|
struct pci_dev *pdev;
|
|
/* sync pci state */
|
|
struct mutex pci_status_mutex;
|
|
enum mlx5_pci_status pci_status;
|
|
u8 rev_id;
|
|
char board_id[MLX5_BOARD_ID_LEN];
|
|
struct mlx5_cmd cmd;
|
|
struct {
|
|
struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
|
|
u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
|
|
u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
|
|
u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
|
|
u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
|
|
u8 embedded_cpu;
|
|
} caps;
|
|
struct mlx5_timeouts *timeouts;
|
|
u64 sys_image_guid;
|
|
phys_addr_t iseg_base;
|
|
struct mlx5_init_seg __iomem *iseg;
|
|
phys_addr_t bar_addr;
|
|
enum mlx5_device_state state;
|
|
/* sync interface state */
|
|
struct mutex intf_state_mutex;
|
|
struct lock_class_key lock_key;
|
|
unsigned long intf_state;
|
|
struct mlx5_priv priv;
|
|
struct mlx5_profile profile;
|
|
u32 issi;
|
|
struct mlx5e_resources mlx5e_res;
|
|
struct mlx5_dm *dm;
|
|
struct mlx5_vxlan *vxlan;
|
|
struct mlx5_geneve *geneve;
|
|
struct {
|
|
struct mlx5_rsvd_gids reserved_gids;
|
|
u32 roce_en;
|
|
} roce;
|
|
#ifdef CONFIG_MLX5_FPGA
|
|
struct mlx5_fpga_device *fpga;
|
|
#endif
|
|
struct mlx5_clock clock;
|
|
struct mlx5_ib_clock_info *clock_info;
|
|
struct mlx5_fw_tracer *tracer;
|
|
struct mlx5_rsc_dump *rsc_dump;
|
|
u32 vsc_addr;
|
|
struct mlx5_hv_vhca *hv_vhca;
|
|
struct mlx5_thermal *thermal;
|
|
};
|
|
|
|
struct mlx5_db {
|
|
__be32 *db;
|
|
union {
|
|
struct mlx5_db_pgdir *pgdir;
|
|
struct mlx5_ib_user_db_page *user_page;
|
|
} u;
|
|
dma_addr_t dma;
|
|
int index;
|
|
};
|
|
|
|
enum {
|
|
MLX5_COMP_EQ_SIZE = 1024,
|
|
};
|
|
|
|
enum {
|
|
MLX5_PTYS_IB = 1 << 0,
|
|
MLX5_PTYS_EN = 1 << 2,
|
|
};
|
|
|
|
typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
|
|
|
|
enum {
|
|
MLX5_CMD_ENT_STATE_PENDING_COMP,
|
|
};
|
|
|
|
struct mlx5_cmd_work_ent {
|
|
unsigned long state;
|
|
struct mlx5_cmd_msg *in;
|
|
struct mlx5_cmd_msg *out;
|
|
void *uout;
|
|
int uout_size;
|
|
mlx5_cmd_cbk_t callback;
|
|
struct delayed_work cb_timeout_work;
|
|
void *context;
|
|
int idx;
|
|
struct completion handling;
|
|
struct completion done;
|
|
struct mlx5_cmd *cmd;
|
|
struct work_struct work;
|
|
struct mlx5_cmd_layout *lay;
|
|
int ret;
|
|
int page_queue;
|
|
u8 status;
|
|
u8 token;
|
|
u64 ts1;
|
|
u64 ts2;
|
|
u16 op;
|
|
bool polling;
|
|
/* Track the max comp handlers */
|
|
refcount_t refcnt;
|
|
};
|
|
|
|
enum phy_port_state {
|
|
MLX5_AAA_111
|
|
};
|
|
|
|
struct mlx5_hca_vport_context {
|
|
u32 field_select;
|
|
bool sm_virt_aware;
|
|
bool has_smi;
|
|
bool has_raw;
|
|
enum port_state_policy policy;
|
|
enum phy_port_state phys_state;
|
|
enum ib_port_state vport_state;
|
|
u8 port_physical_state;
|
|
u64 sys_image_guid;
|
|
u64 port_guid;
|
|
u64 node_guid;
|
|
u32 cap_mask1;
|
|
u32 cap_mask1_perm;
|
|
u16 cap_mask2;
|
|
u16 cap_mask2_perm;
|
|
u16 lid;
|
|
u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
|
|
u8 lmc;
|
|
u8 subnet_timeout;
|
|
u16 sm_lid;
|
|
u8 sm_sl;
|
|
u16 qkey_violation_counter;
|
|
u16 pkey_violation_counter;
|
|
bool grh_required;
|
|
};
|
|
|
|
#define STRUCT_FIELD(header, field) \
|
|
.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
|
|
.struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
|
|
|
|
extern struct dentry *mlx5_debugfs_root;
|
|
|
|
static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->fw_rev) & 0xffff;
|
|
}
|
|
|
|
static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->fw_rev) >> 16;
|
|
}
|
|
|
|
static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
|
|
{
|
|
return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
|
|
}
|
|
|
|
static inline u32 mlx5_base_mkey(const u32 key)
|
|
{
|
|
return key & 0xffffff00u;
|
|
}
|
|
|
|
static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
|
|
{
|
|
return ((u32)1 << log_sz) << log_stride;
|
|
}
|
|
|
|
static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
|
|
u8 log_stride, u8 log_sz,
|
|
u16 strides_offset,
|
|
struct mlx5_frag_buf_ctrl *fbc)
|
|
{
|
|
fbc->frags = frags;
|
|
fbc->log_stride = log_stride;
|
|
fbc->log_sz = log_sz;
|
|
fbc->sz_m1 = (1 << fbc->log_sz) - 1;
|
|
fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
|
|
fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
|
|
fbc->strides_offset = strides_offset;
|
|
}
|
|
|
|
static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
|
|
u8 log_stride, u8 log_sz,
|
|
struct mlx5_frag_buf_ctrl *fbc)
|
|
{
|
|
mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
|
|
}
|
|
|
|
static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
|
|
u32 ix)
|
|
{
|
|
unsigned int frag;
|
|
|
|
ix += fbc->strides_offset;
|
|
frag = ix >> fbc->log_frag_strides;
|
|
|
|
return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
|
|
}
|
|
|
|
static inline u32
|
|
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
|
|
{
|
|
u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
|
|
|
|
return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
|
|
}
|
|
|
|
enum {
|
|
CMD_ALLOWED_OPCODE_ALL,
|
|
};
|
|
|
|
void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
|
|
void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
|
|
void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
|
|
|
|
struct mlx5_async_ctx {
|
|
struct mlx5_core_dev *dev;
|
|
atomic_t num_inflight;
|
|
struct completion inflight_done;
|
|
};
|
|
|
|
struct mlx5_async_work;
|
|
|
|
typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
|
|
|
|
struct mlx5_async_work {
|
|
struct mlx5_async_ctx *ctx;
|
|
mlx5_async_cbk_t user_callback;
|
|
u16 opcode; /* cmd opcode */
|
|
u16 op_mod; /* cmd op_mod */
|
|
void *out; /* pointer to the cmd output buffer */
|
|
};
|
|
|
|
void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
|
|
struct mlx5_async_ctx *ctx);
|
|
void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
|
|
int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
|
|
void *out, int out_size, mlx5_async_cbk_t callback,
|
|
struct mlx5_async_work *work);
|
|
void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
|
|
int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
|
|
int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
|
|
int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
|
|
int out_size);
|
|
|
|
#define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
|
|
({ \
|
|
mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
|
|
MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
|
|
})
|
|
|
|
#define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
|
|
({ \
|
|
u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
|
|
mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
|
|
})
|
|
|
|
int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
|
|
void *out, int out_size);
|
|
bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
|
|
|
|
void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
|
|
void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
|
|
|
|
int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
|
|
void mlx5_health_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_health_init(struct mlx5_core_dev *dev);
|
|
void mlx5_start_health_poll(struct mlx5_core_dev *dev);
|
|
void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
|
|
void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
|
|
void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
|
|
void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
|
|
int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
|
|
struct mlx5_frag_buf *buf, int node);
|
|
void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
|
|
struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
|
|
gfp_t flags, int npages);
|
|
void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
|
|
struct mlx5_cmd_mailbox *head);
|
|
int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
|
|
int inlen);
|
|
int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
|
|
int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
|
|
int outlen);
|
|
int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
|
|
int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
|
|
int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
|
|
void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
|
|
void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
|
|
void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
|
|
void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
|
|
s32 npages, bool ec_function);
|
|
int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
|
|
int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
|
|
void mlx5_register_debugfs(void);
|
|
void mlx5_unregister_debugfs(void);
|
|
|
|
void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
|
|
void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
|
|
int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
|
|
int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
|
|
int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
|
|
|
|
struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
|
|
void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
|
|
void *data_out, int size_out, u16 reg_id, int arg,
|
|
int write, bool verbose);
|
|
int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
|
|
int size_in, void *data_out, int size_out,
|
|
u16 reg_num, int arg, int write);
|
|
|
|
int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
|
|
int node);
|
|
|
|
static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
|
|
{
|
|
return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
|
|
}
|
|
|
|
void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
|
|
|
|
const char *mlx5_command_str(int command);
|
|
void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
|
|
void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
|
|
int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
|
|
int npsvs, u32 *sig_index);
|
|
int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
|
|
__be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
|
|
void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
|
|
int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
|
|
struct mlx5_odp_caps *odp_caps);
|
|
|
|
int mlx5_init_rl_table(struct mlx5_core_dev *dev);
|
|
void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
|
|
int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
|
|
struct mlx5_rate_limit *rl);
|
|
void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
|
|
bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
|
|
int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
|
|
bool dedicated_entry, u16 *index);
|
|
void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
|
|
bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
|
|
struct mlx5_rate_limit *rl_1);
|
|
int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
|
|
bool map_wc, bool fast_path);
|
|
void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
|
|
|
|
unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
|
|
struct cpumask *
|
|
mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
|
|
unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
|
|
int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
|
|
u8 roce_version, u8 roce_l3_type, const u8 *gid,
|
|
const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
|
|
|
|
static inline u32 mlx5_mkey_to_idx(u32 mkey)
|
|
{
|
|
return mkey >> 8;
|
|
}
|
|
|
|
static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
|
|
{
|
|
return mkey_idx << 8;
|
|
}
|
|
|
|
static inline u8 mlx5_mkey_variant(u32 mkey)
|
|
{
|
|
return mkey & 0xff;
|
|
}
|
|
|
|
/* Async-atomic event notifier used by mlx5 core to forward FW
|
|
* evetns received from event queue to mlx5 consumers.
|
|
* Optimise event queue dipatching.
|
|
*/
|
|
int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
|
|
int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
|
|
|
|
/* Async-atomic event notifier used for forwarding
|
|
* evetns from the event queue into the to mlx5 events dispatcher,
|
|
* eswitch, clock and others.
|
|
*/
|
|
int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
|
|
int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
|
|
|
|
/* Blocking event notifier used to forward SW events, used for slow path */
|
|
int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
|
|
int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
|
|
int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
|
|
void *data);
|
|
|
|
int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
|
|
|
|
int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
|
|
int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
|
|
bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
|
|
struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
|
|
u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
|
|
struct net_device *slave);
|
|
int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
|
|
u64 *values,
|
|
int num_counters,
|
|
size_t *offsets);
|
|
struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
|
|
|
|
#define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
|
|
for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
|
|
peer; \
|
|
peer = mlx5_lag_get_next_peer_mdev(dev, &i))
|
|
|
|
u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
|
|
struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
|
|
void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
|
|
int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
|
|
u64 length, u32 log_alignment, u16 uid,
|
|
phys_addr_t *addr, u32 *obj_id);
|
|
int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
|
|
u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
|
|
|
|
struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
|
|
void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
|
|
|
|
int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
|
|
int vf_id,
|
|
struct notifier_block *nb);
|
|
void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
|
|
int vf_id,
|
|
struct notifier_block *nb);
|
|
#ifdef CONFIG_MLX5_CORE_IPOIB
|
|
struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
|
|
struct ib_device *ibdev,
|
|
const char *name,
|
|
void (*setup)(struct net_device *));
|
|
#endif /* CONFIG_MLX5_CORE_IPOIB */
|
|
int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
|
|
struct ib_device *device,
|
|
struct rdma_netdev_alloc_params *params);
|
|
|
|
enum {
|
|
MLX5_PCI_DEV_IS_VF = 1 << 0,
|
|
};
|
|
|
|
static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->coredev_type == MLX5_COREDEV_PF;
|
|
}
|
|
|
|
static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->coredev_type == MLX5_COREDEV_VF;
|
|
}
|
|
|
|
static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->caps.embedded_cpu;
|
|
}
|
|
|
|
static inline bool
|
|
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
|
|
}
|
|
|
|
static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
|
|
{
|
|
return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
|
|
}
|
|
|
|
static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->priv.sriov.max_vfs;
|
|
}
|
|
|
|
static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
|
|
{
|
|
/* LACP owner conditions:
|
|
* 1) Function is physical.
|
|
* 2) LAG is supported by FW.
|
|
* 3) LAG is managed by driver (currently the only option).
|
|
*/
|
|
return MLX5_CAP_GEN(dev, vport_group_manager) &&
|
|
(MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
|
|
MLX5_CAP_GEN(dev, lag_master);
|
|
}
|
|
|
|
static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
|
|
{
|
|
return dev->priv.sriov.max_ec_vfs;
|
|
}
|
|
|
|
static inline int mlx5_get_gid_table_len(u16 param)
|
|
{
|
|
if (param > 4) {
|
|
pr_warn("gid table length is zero\n");
|
|
return 0;
|
|
}
|
|
|
|
return 8 * (1 << param);
|
|
}
|
|
|
|
static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
|
|
{
|
|
return !!(dev->priv.rl_table.max_size);
|
|
}
|
|
|
|
static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
|
|
{
|
|
return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
|
|
MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
|
|
}
|
|
|
|
static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
|
|
{
|
|
return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
|
|
}
|
|
|
|
static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
|
|
{
|
|
return mlx5_core_is_mp_slave(dev) ||
|
|
mlx5_core_is_mp_master(dev);
|
|
}
|
|
|
|
static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
|
|
{
|
|
if (!mlx5_core_mp_enabled(dev))
|
|
return 1;
|
|
|
|
return MLX5_CAP_GEN(dev, native_port_num);
|
|
}
|
|
|
|
static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
|
|
{
|
|
int idx = MLX5_CAP_GEN(dev, native_port_num);
|
|
|
|
if (idx >= 1 && idx <= MLX5_MAX_PORTS)
|
|
return idx - 1;
|
|
else
|
|
return PCI_FUNC(dev->pdev->devfn);
|
|
}
|
|
|
|
enum {
|
|
MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
|
|
};
|
|
|
|
bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
|
|
|
|
static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
|
|
{
|
|
if (MLX5_CAP_GEN(dev, roce_rw_supported))
|
|
return MLX5_CAP_GEN(dev, roce);
|
|
|
|
/* If RoCE cap is read-only in FW, get RoCE state from devlink
|
|
* in order to support RoCE enable/disable feature
|
|
*/
|
|
return mlx5_is_roce_on(dev);
|
|
}
|
|
|
|
enum {
|
|
MLX5_OCTWORD = 16,
|
|
};
|
|
|
|
struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev,
|
|
irqreturn_t (*handler)(int, void *),
|
|
const struct irq_affinity_desc *affdesc,
|
|
const char *name);
|
|
void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map);
|
|
|
|
#endif /* MLX5_DRIVER_H */
|