175 lines
8.4 KiB
JSON
175 lines
8.4 KiB
JSON
[
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "1009",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "20011",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "503",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "101",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "2003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "50021",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
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"PEBS": "2",
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"PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8",
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"SampleAfterValue": "1000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3FBFC00001",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_RFO.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F3FC00002",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of times an RTM execution aborted.",
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"EventCode": "0xc9",
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"EventName": "RTM_RETIRED.ABORTED",
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"PublicDescription": "Counts the number of times RTM abort was triggered.",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of times an RTM execution successfully committed",
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"EventCode": "0xc9",
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"EventName": "RTM_RETIRED.COMMIT",
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"PublicDescription": "Counts the number of times RTM commit succeeded.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of times an RTM execution started.",
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"EventCode": "0xc9",
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"EventName": "RTM_RETIRED.START",
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"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
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"EventCode": "0x54",
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"EventName": "TX_MEM.ABORT_CAPACITY_READ",
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"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
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"SampleAfterValue": "100003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
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"EventCode": "0x54",
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"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
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"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
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"EventCode": "0x54",
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"EventName": "TX_MEM.ABORT_CONFLICT",
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"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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}
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]
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