74 lines
1.9 KiB
Plaintext
74 lines
1.9 KiB
Plaintext
What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
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Date: February 2023
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KernelVersion: 6.4
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Contact: Nava kishore Manne <nava.kishore.manne@amd.com>
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Description: (RO) Read fpga status.
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Read returns a hexadecimal value that tells the current status
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of the FPGA device. Each bit position in the status value is
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described Below(see ug570 chapter 9).
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https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
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====================== ==============================================
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BIT(0) 0: No CRC error
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1: CRC error
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BIT(1) 0: Decryptor security not set
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1: Decryptor security set
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BIT(2) 0: MMCMs/PLLs are not locked
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1: MMCMs/PLLs are locked
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BIT(3) 0: DCI not matched
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1: DCI matched
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BIT(4) 0: Start-up sequence has not finished
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1: Start-up sequence has finished
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BIT(5) 0: All I/Os are placed in High-Z state
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1: All I/Os behave as configured
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BIT(6) 0: Flip-flops and block RAM are write disabled
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1: Flip-flops and block RAM are write enabled
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BIT(7) 0: GHIGH_B_STATUS asserted
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1: GHIGH_B_STATUS deasserted
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BIT(8) to BIT(10) Status of the mode pins
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BIT(11) 0: Initialization has not finished
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1: Initialization finished
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BIT(12) Value on INIT_B_PIN pin
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BIT(13) 0: Signal not released
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1: Signal released
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BIT(14) Value on DONE_PIN pin.
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BIT(15) 0: No IDCODE_ERROR
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1: IDCODE_ERROR
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BIT(16) 0: No SECURITY_ERROR
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1: SECURITY_ERROR
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BIT(17) System Monitor over-temperature if set
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BIT(18) to BIT(20) Start-up state machine (0 to 7)
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Phase 0 = 000
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Phase 1 = 001
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Phase 2 = 011
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Phase 3 = 010
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Phase 4 = 110
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Phase 5 = 111
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Phase 6 = 101
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Phase 7 = 100
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BIT(25) to BIT(26) Indicates the detected bus width
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00 = x1
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01 = x8
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10 = x16
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11 = x32
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====================== ==============================================
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The other bits are reserved.
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