192 lines
4.7 KiB
YAML
192 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8192
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description:
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The Mediatek functional clock controller provides various clocks on MT8192.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8192-scp_adsp
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- mediatek,mt8192-imp_iic_wrap_c
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- mediatek,mt8192-imp_iic_wrap_e
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- mediatek,mt8192-imp_iic_wrap_s
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- mediatek,mt8192-imp_iic_wrap_ws
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- mediatek,mt8192-imp_iic_wrap_w
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- mediatek,mt8192-imp_iic_wrap_n
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- mediatek,mt8192-msdc_top
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- mediatek,mt8192-mfgcfg
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- mediatek,mt8192-imgsys
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- mediatek,mt8192-imgsys2
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- mediatek,mt8192-vdecsys_soc
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- mediatek,mt8192-vdecsys
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- mediatek,mt8192-vencsys
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- mediatek,mt8192-camsys
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- mediatek,mt8192-camsys_rawa
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- mediatek,mt8192-camsys_rawb
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- mediatek,mt8192-camsys_rawc
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- mediatek,mt8192-ipesys
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- mediatek,mt8192-mdpsys
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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scp_adsp: clock-controller@10720000 {
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compatible = "mediatek,mt8192-scp_adsp";
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reg = <0x10720000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_c: clock-controller@11007000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_c";
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reg = <0x11007000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_e: clock-controller@11cb1000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_e";
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reg = <0x11cb1000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_s: clock-controller@11d03000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_s";
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reg = <0x11d03000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_ws: clock-controller@11d23000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_ws";
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reg = <0x11d23000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_w: clock-controller@11e01000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_w";
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reg = <0x11e01000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imp_iic_wrap_n: clock-controller@11f02000 {
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compatible = "mediatek,mt8192-imp_iic_wrap_n";
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reg = <0x11f02000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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msdc_top: clock-controller@11f10000 {
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compatible = "mediatek,mt8192-msdc_top";
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reg = <0x11f10000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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mfgcfg: clock-controller@13fbf000 {
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compatible = "mediatek,mt8192-mfgcfg";
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reg = <0x13fbf000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys: clock-controller@15020000 {
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compatible = "mediatek,mt8192-imgsys";
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reg = <0x15020000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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imgsys2: clock-controller@15820000 {
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compatible = "mediatek,mt8192-imgsys2";
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reg = <0x15820000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys_soc: clock-controller@1600f000 {
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compatible = "mediatek,mt8192-vdecsys_soc";
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reg = <0x1600f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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vdecsys: clock-controller@1602f000 {
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compatible = "mediatek,mt8192-vdecsys";
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reg = <0x1602f000 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: clock-controller@17000000 {
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compatible = "mediatek,mt8192-vencsys";
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reg = <0x17000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys: clock-controller@1a000000 {
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compatible = "mediatek,mt8192-camsys";
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reg = <0x1a000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawa: clock-controller@1a04f000 {
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compatible = "mediatek,mt8192-camsys_rawa";
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reg = <0x1a04f000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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camsys_rawb: clock-controller@1a06f000 {
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compatible = "mediatek,mt8192-camsys_rawb";
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reg = <0x1a06f000 0x1000>;
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#clock-cells = <1>;
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};
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camsys_rawc: clock-controller@1a08f000 {
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compatible = "mediatek,mt8192-camsys_rawc";
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reg = <0x1a08f000 0x1000>;
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#clock-cells = <1>;
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};
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ipesys: clock-controller@1b000000 {
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compatible = "mediatek,mt8192-ipesys";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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mdpsys: clock-controller@1f000000 {
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compatible = "mediatek,mt8192-mdpsys";
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reg = <0x1f000000 0x1000>;
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#clock-cells = <1>;
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};
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