222 lines
5.3 KiB
YAML
222 lines
5.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Video Input controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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$nodename:
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pattern: "^vi@[0-9a-f]+$"
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compatible:
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oneOf:
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- const: nvidia,tegra20-vi
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- const: nvidia,tegra30-vi
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- const: nvidia,tegra114-vi
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- const: nvidia,tegra124-vi
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- items:
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- const: nvidia,tegra132-vi
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- const: nvidia,tegra124-vi
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- const: nvidia,tegra210-vi
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- const: nvidia,tegra186-vi
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- const: nvidia,tegra194-vi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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items:
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- description: module reset
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reset-names:
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items:
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- const: vi
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iommus:
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maxItems: 1
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interconnects:
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minItems: 4
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maxItems: 5
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interconnect-names:
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minItems: 4
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maxItems: 5
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operating-points-v2: true
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power-domains:
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items:
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- description: phandle to the VENC power domain
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges:
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maxItems: 1
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avdd-dsi-csi-supply:
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description: DSI/CSI power supply. Must supply 1.2 V.
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vip:
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$ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Input from the VIP (parallel input capture) module
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patternProperties:
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"^csi@[0-9a-f]+$":
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type: object
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra20-vi
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- nvidia,tegra30-vi
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- nvidia,tegra114-vi
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- nvidia,tegra124-vi
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then:
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required:
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- resets
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- reset-names
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else:
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required:
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- power-domains
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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camera@48 {
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compatible = "aptina,mt9v111";
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reg = <0x48>;
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clocks = <&camera_clk>;
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port {
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mt9v111_out: endpoint {
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remote-endpoint = <&vi_vip_in>;
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};
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};
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};
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};
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vi@54080000 {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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resets = <&tegra_car 100>;
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reset-names = "vi";
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vip {
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compatible = "nvidia,tegra20-vip";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vi_vip_in: endpoint {
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remote-endpoint = <&mt9v111_out>;
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};
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};
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port@1 {
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reg = <1>;
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vi_vip_out: endpoint {
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remote-endpoint = <&vi_in>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vi_in: endpoint {
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remote-endpoint = <&vi_vip_out>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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vi@54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x54080000 0x00000700>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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clocks = <&tegra_car TEGRA210_CLK_VI>;
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power-domains = <&pd_venc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x54080000 0x2000>;
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csi@838 {
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compatible = "nvidia,tegra210-csi";
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reg = <0x838 0x1300>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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assigned-clock-rates = <102000000>,
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<102000000>,
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<102000000>,
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<972000000>;
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clocks = <&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
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power-domains = <&pd_sor>;
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};
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};
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