119 lines
2.9 KiB
YAML
119 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Layerscape External Interrupt Controller
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maintainers:
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- Shawn Guo <shawnguo@kernel.org>
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- Li Yang <leoyang.li@nxp.com>
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description: |
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Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
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LX216xA) support inverting the polarity of certain external interrupt
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lines.
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,ls1021a-extirq
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- fsl,ls1043a-extirq
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- fsl,ls1088a-extirq
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- items:
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- enum:
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- fsl,ls1046a-extirq
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- const: fsl,ls1043a-extirq
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- items:
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- enum:
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- fsl,ls2080a-extirq
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- fsl,lx2160a-extirq
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- const: fsl,ls1088a-extirq
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'#interrupt-cells':
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const: 2
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'#address-cells':
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const: 0
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interrupt-controller: true
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reg:
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maxItems: 1
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description:
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Specifies the Interrupt Polarity Control Register (INTPCR) in the
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SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
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interrupt-map:
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description: Specifies the mapping from external interrupts to GIC interrupts.
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interrupt-map-mask: true
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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- interrupt-map
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- interrupt-map-mask
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,ls1021a-extirq
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then:
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properties:
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interrupt-map:
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minItems: 6
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maxItems: 6
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interrupt-map-mask:
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items:
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- const: 0x7
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- const: 0
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,ls1043a-extirq
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- fsl,ls1046a-extirq
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- fsl,ls1088a-extirq
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- fsl,ls2080a-extirq
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- fsl,lx2160a-extirq
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then:
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properties:
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interrupt-map:
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minItems: 12
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maxItems: 12
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interrupt-map-mask:
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items:
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- const: 0xf
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- const: 0
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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interrupt-controller@1ac {
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compatible = "fsl,ls1021a-extirq";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1ac 4>;
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interrupt-map =
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<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0x7 0x0>;
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};
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