74 lines
1.7 KiB
YAML
74 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip External Interrupt Controller
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maintainers:
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- Claudiu Beznea <claudiu.beznea@microchip.com>
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description:
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This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
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support for handling up to 2 external interrupt lines.
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properties:
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compatible:
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enum:
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- microchip,sama7g5-eic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the input IRQ number (between 0 and 1), the second cell
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is the trigger type as defined in interrupt.txt present in this directory.
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interrupts:
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description: |
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Contains the GIC SPI IRQs mapped to the external interrupt lines. They
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should be specified sequentially from output 0 to output 1.
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minItems: 2
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maxItems: 2
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clocks:
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maxItems: 1
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clock-names:
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const: pclk
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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eic: interrupt-controller@e1628000 {
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compatible = "microchip,sama7g5-eic";
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reg = <0xe1628000 0x100>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
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clock-names = "pclk";
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};
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...
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