157 lines
3.7 KiB
YAML
157 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm PL35x Series Static Memory Controller (SMC)
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: |
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The PL35x Static Memory Controller is a bus where you can connect two kinds
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of memory interfaces, which are NAND and memory mapped interfaces (such as
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SRAM or NOR) depending on the specific configuration.
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The TRM is available here:
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https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
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# We need a select here so we don't match all nodes with 'arm,primecell'
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select:
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properties:
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compatible:
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contains:
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enum:
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- arm,pl353-smc-r2p1
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- arm,pl354
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required:
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- compatible
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properties:
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$nodename:
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pattern: "^memory-controller@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- arm,pl353-smc-r2p1
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- arm,pl354
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- const: arm,primecell
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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reg:
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items:
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- description:
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Configuration registers for the host and sub-controllers.
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The three chip select regions are defined in 'ranges'.
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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ranges:
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minItems: 1
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maxItems: 8
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interrupts:
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minItems: 1
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items:
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- description: Combined or Memory interface 0 IRQ
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- description: Memory interface 1 IRQ
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patternProperties:
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"@[0-7],[a-f0-9]+$":
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type: object
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additionalProperties: true
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description: |
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The child device node represents the controller connected to the SMC
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bus. The controller can be a NAND controller or a pair of any memory
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mapped controllers such as NOR and SRAM controllers.
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properties:
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compatible:
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description:
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Compatible of memory controller.
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reg:
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items:
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- items:
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- description: |
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Chip-select ID, as in the parent range property.
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minimum: 0
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maximum: 7
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- description: |
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Offset of the memory region requested by the device.
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- description: |
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Length of the memory region requested by the device.
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required:
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- compatible
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- reg
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required:
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- compatible
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- reg
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- clock-names
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: arm,pl354
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then:
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properties:
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clocks:
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# According to TRM, really should be 3 clocks
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maxItems: 1
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clock-names:
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const: apb_pclk
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else:
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properties:
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clocks:
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items:
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- description: clock for the memory device bus
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- description: main clock of the SMC
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clock-names:
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items:
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- const: memclk
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- const: apb_pclk
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examples:
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- |
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smcc: memory-controller@e000e000 {
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compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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reg = <0xe000e000 0x0001000>;
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clock-names = "memclk", "apb_pclk";
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clocks = <&clkc 11>, <&clkc 44>;
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ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
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0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
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0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
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#address-cells = <2>;
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#size-cells = <1>;
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nfc0: nand-controller@0,0 {
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compatible = "arm,pl353-nand-r2p1";
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reg = <0 0 0x1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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