51 lines
1.2 KiB
YAML
51 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton NPCM Memory Controller
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maintainers:
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- Marvin Lin <kflin@nuvoton.com>
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- Stanley Chu <yschu@nuvoton.com>
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description: |
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The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
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check).
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The memory controller supports single bit error correction, double bit error
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detection (in-line ECC in which a section (1/8th) of the memory device used to
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store data is used for ECC storage).
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Note, the bootloader must configure ECC mode for the memory controller.
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properties:
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compatible:
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enum:
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- nuvoton,npcm750-memory-controller
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- nuvoton,npcm845-memory-controller
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mc: memory-controller@f0824000 {
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compatible = "nuvoton,npcm750-memory-controller";
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reg = <0xf0824000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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};
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