159 lines
3.8 KiB
YAML
159 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Renesas RZ/N1 Advanced 5 ports ethernet switch
|
|
|
|
maintainers:
|
|
- Clément Léger <clement.leger@bootlin.com>
|
|
|
|
description: |
|
|
The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
|
|
handles 4 ports + 1 CPU management port.
|
|
|
|
allOf:
|
|
- $ref: dsa.yaml#/$defs/ethernet-ports
|
|
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- enum:
|
|
- renesas,r9a06g032-a5psw
|
|
- const: renesas,rzn1-a5psw
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
items:
|
|
- description: Device Level Ring (DLR) interrupt
|
|
- description: Switch interrupt
|
|
- description: Parallel Redundancy Protocol (PRP) interrupt
|
|
- description: Integrated HUB module interrupt
|
|
- description: Receive Pattern Match interrupt
|
|
|
|
interrupt-names:
|
|
items:
|
|
- const: dlr
|
|
- const: switch
|
|
- const: prp
|
|
- const: hub
|
|
- const: ptrn
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
mdio:
|
|
$ref: /schemas/net/mdio.yaml#
|
|
unevaluatedProperties: false
|
|
|
|
clocks:
|
|
items:
|
|
- description: AHB clock used for the switch register interface
|
|
- description: Switch system clock
|
|
|
|
clock-names:
|
|
items:
|
|
- const: hclk
|
|
- const: clk
|
|
|
|
ethernet-ports:
|
|
type: object
|
|
properties:
|
|
'#address-cells':
|
|
const: 1
|
|
'#size-cells':
|
|
const: 0
|
|
|
|
patternProperties:
|
|
"^(ethernet-)?port@[0-4]$":
|
|
type: object
|
|
description: Ethernet switch ports
|
|
|
|
properties:
|
|
pcs-handle:
|
|
maxItems: 1
|
|
description:
|
|
phandle pointing to a PCS sub-node compatible with
|
|
renesas,rzn1-miic.yaml#
|
|
|
|
unevaluatedProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- clock-names
|
|
- power-domains
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
switch@44050000 {
|
|
compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
|
|
reg = <0x44050000 0x10000>;
|
|
clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
|
|
clock-names = "hclk", "clk";
|
|
power-domains = <&sysctrl>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
|
|
|
|
dsa,member = <0 0>;
|
|
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
label = "lan0";
|
|
phy-handle = <&switch0phy3>;
|
|
pcs-handle = <&mii_conv4>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
label = "lan1";
|
|
phy-handle = <&switch0phy1>;
|
|
pcs-handle = <&mii_conv3>;
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
ethernet = <&gmac2>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
|
|
reset-delay-us = <15>;
|
|
clock-frequency = <2500000>;
|
|
|
|
switch0phy1: ethernet-phy@1{
|
|
reg = <1>;
|
|
};
|
|
|
|
switch0phy3: ethernet-phy@3{
|
|
reg = <3>;
|
|
};
|
|
};
|
|
};
|