118 lines
3.6 KiB
YAML
118 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MotorComm yt8xxx Ethernet PHY
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maintainers:
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- Frank Sae <frank.sae@motor-comm.com>
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allOf:
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- $ref: ethernet-phy.yaml#
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properties:
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compatible:
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enum:
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- ethernet-phy-id4f51.e91a
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- ethernet-phy-id4f51.e91b
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rx-internal-delay-ps:
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description: |
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RGMII RX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
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1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
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2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
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default: 1950
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tx-internal-delay-ps:
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description: |
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RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
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enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
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1950, 2100, 2250 ]
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default: 1950
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motorcomm,clk-out-frequency-hz:
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description: clock output on clock output pin.
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enum: [0, 25000000, 125000000]
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default: 0
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motorcomm,keep-pll-enabled:
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description: |
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If set, keep the PLL enabled even if there is no link. Useful if you
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want to use the clock output without an ethernet link.
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type: boolean
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motorcomm,auto-sleep-disabled:
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description: |
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If set, PHY will not enter sleep mode and close AFE after unplug cable
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for a timer.
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type: boolean
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motorcomm,tx-clk-adj-enabled:
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description: |
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This configuration is mainly to adapt to VF2 with JH7110 SoC.
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Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
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type: boolean
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motorcomm,tx-clk-10-inverted:
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description: |
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Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
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Transmit PHY Clock delay train configuration when speed is 10Mbps.
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type: boolean
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motorcomm,tx-clk-100-inverted:
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description: |
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Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
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Transmit PHY Clock delay train configuration when speed is 100Mbps.
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type: boolean
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motorcomm,tx-clk-1000-inverted:
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description: |
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Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
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Transmit PHY Clock delay train configuration when speed is 1000Mbps.
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type: boolean
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii-id";
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ethernet-phy@4 {
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/* Only needed to make DT lint tools work. Do not copy/paste
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* into real DTS files.
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*/
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compatible = "ethernet-phy-id4f51.e91a";
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reg = <4>;
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rx-internal-delay-ps = <2100>;
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tx-internal-delay-ps = <150>;
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motorcomm,clk-out-frequency-hz = <0>;
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motorcomm,keep-pll-enabled;
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motorcomm,auto-sleep-disabled;
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};
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};
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii";
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ethernet-phy@5 {
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/* Only needed to make DT lint tools work. Do not copy/paste
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* into real DTS files.
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*/
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compatible = "ethernet-phy-id4f51.e91a";
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reg = <5>;
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motorcomm,clk-out-frequency-hz = <125000000>;
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motorcomm,keep-pll-enabled;
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motorcomm,auto-sleep-disabled;
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};
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};
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