254 lines
7.1 KiB
YAML
254 lines
7.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT6779 Pin Controller
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maintainers:
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- Andy Teng <andy.teng@mediatek.com>
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- Sean Wang <sean.wang@kernel.org>
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description:
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The MediaTek pin controller on MT6779 is used to control pin functions, pull
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up/down resistance and drive strength options.
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properties:
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compatible:
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enum:
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- mediatek,mt6779-pinctrl
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- mediatek,mt6797-pinctrl
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reg:
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description: Physical addresses for GPIO base(s) and EINT registers.
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reg-names: true
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gpio-controller: true
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"#gpio-cells":
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const: 2
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description:
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Number of cells in GPIO specifier. Since the generic GPIO binding is used,
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the amount of cells must be specified as 2. See the below mentioned gpio
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binding representation for description of particular cells.
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gpio-ranges:
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minItems: 1
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maxItems: 5
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description:
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GPIO valid number range.
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interrupt-controller: true
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interrupts:
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maxItems: 1
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description:
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Specifies the summary IRQ.
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"#interrupt-cells":
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const: 2
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required:
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- compatible
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- reg
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- reg-names
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- gpio-controller
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- "#gpio-cells"
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allOf:
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- $ref: pinctrl.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt6779-pinctrl
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then:
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properties:
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reg:
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minItems: 9
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maxItems: 9
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reg-names:
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items:
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- const: gpio
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- const: iocfg_rm
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- const: iocfg_br
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- const: iocfg_lm
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- const: iocfg_lb
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- const: iocfg_rt
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- const: iocfg_lt
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- const: iocfg_tl
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- const: eint
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt6797-pinctrl
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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reg-names:
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items:
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- const: gpio
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- const: iocfgl
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- const: iocfgb
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- const: iocfgr
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- const: iocfgt
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- if:
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properties:
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reg-names:
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contains:
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const: eint
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then:
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required:
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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patternProperties:
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'-[0-9]*$':
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type: object
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additionalProperties: false
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patternProperties:
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'-pins*$':
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type: object
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description:
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input
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schmitt.
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$ref: /schemas/pinctrl/pincfg-node.yaml
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properties:
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pinmux:
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description:
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Integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are
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defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
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bias-disable: true
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bias-pull-up: true
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bias-pull-down: true
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input-enable: true
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input-disable: true
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output-low: true
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output-high: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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drive-strength:
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enum: [2, 4, 8, 12, 16]
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slew-rate:
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enum: [0, 1]
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mediatek,pull-up-adv:
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description: |
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Pull up setings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as
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below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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mediatek,pull-down-adv:
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description: |
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Pull down settings for 2 pull resistors, R0 and R1. User can
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configure those special pins. Valid arguments are described as
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below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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required:
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- pinmux
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additionalProperties: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6779-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11c20000 0 0x1000>,
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<0 0x11d10000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e70000 0 0x1000>,
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<0 0x11ea0000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11f30000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rm",
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"iocfg_br", "iocfg_lm",
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"iocfg_lb", "iocfg_rt",
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"iocfg_lt", "iocfg_tl",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 210>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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mmc0_pins_default: mmc0-0 {
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cmd-dat-pins {
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pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
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<PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
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<PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
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<PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
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<PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
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<PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
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<PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
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<PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
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<PINMUX_GPIO167__FUNC_MSDC0_CMD>;
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input-enable;
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mediatek,pull-up-adv = <1>;
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};
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clk-pins {
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pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
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mediatek,pull-down-adv = <2>;
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};
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rst-pins {
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pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
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mediatek,pull-up-adv = <0>;
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};
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};
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};
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mmc0 {
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-names = "default";
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};
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};
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