122 lines
3.5 KiB
YAML
122 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
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properties:
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compatible:
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const: qcom,ipq9574-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 33
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gpio-line-names:
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maxItems: 65
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq9574-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq9574-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-ipq9574-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
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minItems: 1
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maxItems: 8
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
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audio_pdm0, audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
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blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
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blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
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blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
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cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
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gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
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pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake,
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prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm,
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qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
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qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
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qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
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qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
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qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
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rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
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wci20, wci21, wsa_swrm ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq9574-tlmm";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 65>;
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uart2-state {
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pins = "gpio34", "gpio35";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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