156 lines
5.0 KiB
YAML
156 lines
5.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm MSM8994 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
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properties:
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compatible:
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enum:
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- qcom,msm8992-pinctrl
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- qcom,msm8994-pinctrl
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 73
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gpio-line-names:
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maxItems: 146
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-msm8994-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-msm8994-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-msm8994-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
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sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
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blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
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blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
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blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
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blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
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blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
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blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
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blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
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blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
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blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
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blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
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blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
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blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
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blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
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cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
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cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
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cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
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gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
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gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
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gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
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hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
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qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
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qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
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qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
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qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
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qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
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pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
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tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,msm8994-pinctrl";
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reg = <0xfd510000 0x4000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 146>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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blsp1-uart2-default-state {
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function = "blsp_uart2";
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pins = "gpio4", "gpio5";
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drive-strength = <16>;
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bias-disable;
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};
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blsp1-spi1-default-state {
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default-pins {
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pins = "gpio0", "gpio1", "gpio3";
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function = "blsp_spi1";
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drive-strength = <10>;
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bias-pull-down;
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};
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cs-pins {
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pins = "gpio8";
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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